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IS43DR81280C の電気的特性と機能

IS43DR81280CのメーカーはISSIです、この部品の機能は「DDR2 DRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS43DR81280C
部品説明 DDR2 DRAM
メーカ ISSI
ロゴ ISSI ロゴ 




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IS43DR81280C Datasheet, IS43DR81280C PDF,ピン配置, 機能
IS43/46DR81280C
IS43/46DR16640C
128Mx8, 64Mx16 DDR2 DRAM
FEATURES
Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Double data rate interface: two data transfers
per clock cycle
Differential data strobe (DQS, DQS)
4-bit prefetch architecture
On chip DLL to align DQ and DQS transitions
with CK
8 internal banks for concurrent operation
Programmable CAS latency (CL) 3, 4, 5, 6 and 7
supported
Posted CAS and programmable additive latency
(AL) 0, 1, 2, 3, 4, 5 and 6 supported
WRITE latency = READ latency - 1 tCK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength, full and
reduced strength options
On-die termination (ODT)
ADVANCED INFORMATION
DESCRIPTION
MAY 2013
ISSI's 1Gb DDR2 SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The
double-data rate architecture is essentially a 4n-prefetch
architecture, with an interface designed to transfer two
data words per clock cycle at the I/O balls.
ADDRESS TABLE
Parameter
Configuration
Refresh Count
128M x 8
16M x 8 x 8
banks
8K/64ms
64M x 16
8M x 16 x 8
banks
8K/64ms
Row Addressing 16K (A0-A13) 8K (A0-A12)
Column
Addressing
1K (A0-A9)
Bank Addressing BA0 - BA2
1K (A0-A9)
BA0 - BA2
Precharge
Addressing
A10
A10
OPTIONS
Configuration(s):
128Mx8 (16Mx8x8 banks): IS43/46DR81280C
64Mx16 (8Mx16x8 banks): IS43/46DR16640C
Package:
x8: 60-ball BGA (8mm x 10.5mm)
x16: 84-ball WBGA (8mm x 12.5mm)
Timing – Cycle time
2.5ns @CL=5 DDR2-800D
2.5ns @CL=6 DDR2-800E
3.0ns @CL=5 DDR2-667D
3.75ns @CL=4 DDR2-533C
5ns @CL=3 DDR2-400B
Temperature Range:
Commercial (0°C Tc 85°C)
Industrial (-40°C Tc 95°C; -40°C Ta 85°C)
Automotive, A1 (-40°C Tc 95°C; -40°C Ta 85°C)
Automotive, A2 (-40°C Tc; Ta 105°C)
Tc = Case Temp, Ta = Ambient Temp
KEY TIMING PARAMETERS
Speed Grade -25D -3D
tRCD
12.5 15
tRP 12.5 15
tRC 55 55
tRAS
40 40
tCK @CL=3
55
tCK @CL=4
3.75 3.75
tCK @CL=5
2.5 3
tCK @CL=6
2.5 —
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest
version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. 00A
6/4/2013

1 Page





IS43DR81280C pdf, ピン配列
IS43/46DR81280C, IS43/46DR16640C
PIN DESCRIPTION TABLE
Symbol
CK, CK
CKE
Type
Input
Input
Function
Clock: CK and CK are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CK and negative edge of CK.
Output (read) data is referenced to the crossings of CK and CK (both directions of
crossing).
Clock Enable: CKE HIGH activates, and CKE LOW deactivates, internal clock signals
and device input buffers and output drivers. Taking CKE LOW provides Precharge
Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row
Active in any bank). CKE is synchronous for power down entry and exit, and for self
refresh entry. CKE is asynchronous for self refresh exit. After VREF has become
stable during the power on and initialization sequence, it must be maintained for
proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF
must be maintained to this input. CKE must be maintained HIGH throughout read and
write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during
power-down. Input buffers, excluding CKE, are disabled during self refresh.
CS
ODT
Input
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for
external Rank selection on systems with multiple Ranks. CS is considered part of the
command code.
On Die Termination: ODT (registered HIGH) enables termination resistance internal
to the DDR2 SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS, DM
signals. The ODT pin will be ignored if the EMR(1) is programmed to disable ODT.
RAS, CAS, WE Input
DM (x8) or
UDM, LDM (x16)
Input
BA0 - BA2
Input
A0 - A13
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being
entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH coincident with that input data during a Write access. DM
is sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading. For x8, the function of DM is enabled by EMRS
command to EMR(1) [A11].
Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or
Precharge command is being applied. Bank address also determines if the mode
register or one of the extended mode registers is to be accessed during a MRS or
EMRS command cycle.
Address Inputs: Provide the row address for Active commands and the column
address and Auto Precharge bit for Read/Write commands to select one location
out of the memory array in the respective bank. A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW) or all
banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0 -
BA2. The address inputs also provide the op-code during MRS or EMRS commands.
Integrated Silicon Solution, Inc. — www.issi.com 3
Rev. 00A
6/4/2013


3Pages


IS43DR81280C 電子部品, 半導体
IS43/46DR81280C, IS43/46DR16640C
PIN CONFIGURATION
PACKAGE CODE: B 84 BALL FBGA (Top View) (8.00 mm x 12.50 mm Body, 0.8 mm Ball Pitch)
123456789
A
VDD NC VSS
B
C DQ14 VSSQ UDM
VDDQ DQ9 VDDQ
D
DQ12 VSSQ DQ11
E
F VDD NC VSS
DQ6 VSSQ LDM
G
H VDDQ DQ1 VDDQ
J DQ4 VSSQ DQ3
VDDL VREF VSS
K
CKE WE
L
M BA2 BA0 BA1
N VSS A10/AP A1
P A3 A5
R VDD A7 A9
A12 NC
Pin name
A0 to A12
BA0 to BA2
DQ0 to DQ15
LDQS, UDQS
/LDQS, /UDQS
/CS
/RAS, /CAS, /WE
CKE
CK, /CK
LDM to UDM
Function
Address inputs
Bank select
Data input/output
Differential data strobe
Chip select
Command input
Clock enable
Differential clock input
Write data mask
6
VSSQ UDQS VDDQ
UDQS VSSQ DQ15
VDDQ DQ8 VDDQ
DQ10 VSSQ DQ13
VSSQ LDQS VDDQ
LDQS VSSQ DQ7
VDDQ DQ0 VDDQ
DQ2 VSSQ DQ5
VSSDL CK VDD
RAS CK ODT
CAS CS
A2 A0 VDD
A6 A4
A11 A8 VSS
NC NC
Not populated
Pin name
ODT
VDD
VSS
VDDQ
Function
ODT control
Supply voltage for internal circuit
Ground for internal circuit
Supply voltage for DQ circuit
VSSQ
VREF
VDDL
VSSDL
NC
Ground for DQ circuit
Input reference voltage
Supply voltage for DLL circuit
Ground for DLL circuit
No connection
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
6/4/2013

6 Page



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部品番号部品説明メーカ
IS43DR81280C

DDR2 DRAM

ISSI
ISSI


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