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IS45S83200J の電気的特性と機能

IS45S83200JのメーカーはISSIです、この部品の機能は「256Mb SYNCHRONOUS DRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS45S83200J
部品説明 256Mb SYNCHRONOUS DRAM
メーカ ISSI
ロゴ ISSI ロゴ 




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IS45S83200J Datasheet, IS45S83200J PDF,ピン配置, 機能
IS42S83200J, IS42S16160J
IS45S83200J, IS45S16160J
32Meg x 8, 16Meg x16
256Mb SYNCHRONOUS DRAM
ADVANCED INFORMATION
MARCH 2013
FEATURES
• Clock frequency: 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single Power supply: 3.3V + 0.3V
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh
• 8K refresh cycles every 32 ms (A2 grade) or
64 ms (commercial, industrial, A1 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
OPTIONS
• Package:
54-pin TSOP-II
54-ball BGA
• Operating Temperature Range:
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
Automotive Grade A1 (-40oC to +85oC)
Automotive Grade A2 (-40oC to +105oC)
OVERVIEW
ISSI's 256Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
The 256Mb SDRAM is organized as follows.
IS42S83200G IS42S16160G
8M x 8 x 4 Banks 4M x16x4 Banks
54-pin TSOPII 54-pin TSOPII
54-ball BGA
54-ball BGA
KEY TIMING PARAMETERS
Parameter -6 -7 Unit
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
6 7 ns
10 7.5 ns
Clk Frequency
CAS Latency = 3
CAS Latency = 2
166 143 Mhz
100 133 Mhz
Access Time from Clock
CAS Latency = 3
5.4 5.4 ns
CAS Latency = 2
5.4 5.4 ns
ADDRESS TABLE
Parameter
32M x 8
Configuration
8M x 8 x 4
banks
Refresh Count
Com./Ind.
A1
A2
8K/64ms
8K/64ms
8K/32ms
Row Addresses
A0-A12
Column Addresses
A0-A9
Bank Address Pins
BA0, BA1
Auto Precharge Pins
A10/AP
16M x 16
4M x 16 x 4
banks
8K/64ms
8K/64ms
8K/32ms
A0-A12
A0-A8
BA0, BA1
A10/AP
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such ap-
plications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. 00B
3/19/2013

1 Page





IS45S83200J pdf, ピン配列
IS42S83200J, IS42S16160J
IS45S83200J, IS45S16160J
PIN CONFIGURATIONS
54 pin TSOP - Type II for x8
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDD
NC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS
53 DQ7
52 VSSQ
51 NC
50 DQ6
49 VDDQ
48 NC
47 DQ5
46 VSSQ
45 NC
44 DQ4
43 VDDQ
42 NC
41 VSS
40 NC
39 DQM
38 CLK
37 CKE
36 A12
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
PIN DESCRIPTIONS
A0-A12
Row Address Input
A0-A9
Column Address Input
BA0, BA1
Bank Select Address
DQ0 to DQ7 Data I/O
CLK
System Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe Command
CAS Column Address Strobe Command
WE Write Enable
DQM Data Input/Output Mask
Vdd Power
Vss Ground
Vddq Power Supply for I/O Pin
Vssq Ground for I/O Pin
NC No Connection
Integrated Silicon Solution, Inc. — www.issi.com 3
Rev. 00B
3/19/2013


3Pages


IS45S83200J 電子部品, 半導体
IS42S83200J, IS42S16160J
IS45S83200J, IS45S16160J
PIN CONFIGURATION
54-ball TF-BGA for x16 (Top View) (8.00 mm x 8.00 mm Body, 0.8 mm Ball Pitch)
package code: B
1 2 3 4 5 6 7 8 9
A
B VSS DQ15 VSSQ
C DQ14 DQ13 VDDQ
D DQ12 DQ11 VSSQ
E DQ10 DQ9 VDDQ
F DQ8 NC VSS
G DQMH CLK CKE
H A12 A11 A9
J A8 A7 A6
VSS A5 A4
VDDQ DQ0 VDD
VSSQ DQ2 DQ1
VDDQ DQ4 DQ3
VSSQ DQ6 DQ5
VDD DQML DQ7
CAS RAS WE
BA0 BA1 CS
A0 A1 A10
A3 A2 VDD
PIN DESCRIPTIONS
A0-A12
Row Address Input
A0-A8
Column Address Input
BA0, BA1
Bank Select Address
DQ0 to DQ15 Data I/O
CLK
System Clock Input
CKE
Clock Enable
CS Chip Select
RAS
Row Address Strobe Command
CAS
Column Address Strobe Command
6
WE
DQML
DQMH
Vdd
Vss
Vddq
Vssq
NC
Write Enable
x16 Lower Byte Input/Output Mask
x16 Upper Byte Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
3/19/2013

6 Page



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共有リンク

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部品番号部品説明メーカ
IS45S83200C

256 Mb Single Data Rate Synchronous DRAM

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IS45S83200D

256-MBIT SYNCHRONOUS DRAM

Integrated Silicon Solution
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IS45S83200J

256Mb SYNCHRONOUS DRAM

ISSI
ISSI


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