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IS25LQ512B の電気的特性と機能

IS25LQ512BのメーカーはISSIです、この部品の機能は「3V QUAD SERIAL FLASH MEMORY」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS25LQ512B
部品説明 3V QUAD SERIAL FLASH MEMORY
メーカ ISSI
ロゴ ISSI ロゴ 




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IS25LQ512B Datasheet, IS25LQ512B PDF,ピン配置, 機能
IS25LQ025B
IS25LQ512B
IS25LQ010B
IS25LQ020B
IS25LQ040B
256K/512K/1M/2M/4MBIT
3V QUAD SERIAL FLASH MEMORY WITH
MULTI-I/O SPI

1 Page





IS25LQ512B pdf, ピン配列
IS25LQ025/512/010/020/040B
TABLE OF CONTENTS
FEATURES ..........................................................................................................................................................2
GENERAL DESCRIPTION...................................................................................................................................2
1. PIN CONFIGURATION ................................................................................................................................5
2. PIN DESCRIPTIONS....................................................................................................................................6
3. BLOCK DIAGRAM........................................................................................................................................7
4. SPI MODES DESCRIPTION ........................................................................................................................8
5. SYSTEM CONFIGURATION......................................................................................................................10
5.1 BLOCK/SECTOR ADDRESSES...........................................................................................................10
6. REGISTERS ...............................................................................................................................................12
6.1. STATUS REGISTER............................................................................................................................12
6.2. FUNCTION REGISTER .......................................................................................................................15
7. PROTECTION MODE ................................................................................................................................16
7.1 HARDWARE WRITE PROTECTION....................................................................................................16
7.2 SOFTWARE WRITE PROTECTION ....................................................................................................16
8. DEVICE OPERATION ................................................................................................................................17
8.1 READ DATA OPERATION (RD, 03h)...................................................................................................18
8.2 FAST READ DATA OPERATION (FR, 0Bh) ........................................................................................20
8.3 HOLD OPERATION ..............................................................................................................................21
8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh)............................................................................21
8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh)...................................................................24
8.6 FAST READ QUAD OUTPUT (FRQO, 6Bh) ........................................................................................26
8.7 FAST READ QUAD I/O OPERATION (FRQIO, EBh)...........................................................................28
8.8 PAGE PROGRAM OPERATION (PP, 02h) ..........................................................................................30
8.9 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 38h)................................................................31
8.10 ERASE OPERATION..........................................................................................................................32
8.11 SECTOR ERASE OPERATION (SER, D7h/20h) ...............................................................................32
8.12 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h).............................................................33
8.13 CHIP ERASE OPERATION (CER, C7h/60h) .....................................................................................34
8.14 WRITE ENABLE OPERATION (WREN, 06h).....................................................................................35
8.15 WRITE DISABLE OPERATION (WRDI, 04h) .....................................................................................35
8.16 READ STATUS REGISTER OPERATION (RDSR, 05h) ...................................................................36
8.17 WRITE STATUS REGISTER OPERATION (WRSR, 01h) .................................................................36
8.18 READ FUNCTION REGISTER OPERATION (RDFR, 48h) ...............................................................37
8.19 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h).............................................................37
8.20 PROGRAM/ERASE SUSPEND & RESUME ......................................................................................38
8.21 DEEP POWER DOWN (DP, B9h) ......................................................................................................39
8.22 RELEASE DEEP POWER DOWN (RDPD, ABh) ...............................................................................41
Integrated Silicon Solution, Inc.- www.issi.com
Rev.A
12/12/2014
3


3Pages


IS25LQ512B 電子部品, 半導体
IS25LQ025/512/010/020/040B
2. PIN DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
Chip Enable: The Chip Enable (CE#) pin enables and disables the devices operation.
When CE# is high the device is deselected and output pins are in a high impedance
state. When deselected the devices non-critical internal circuitry power down to allow
minimal levels of power consumption while in a standby state.
CE#
INPUT
When CE# is pulled low the device will be selected and brought out of standby mode.
The device is considered active and instructions can be written to, data read, and
written to the device. After power-up, CE# must transition from high to low before a
new instruction will be accepted.
Keeping CE# in a high state deselects the device and switches it into its low power
state. Data will not be accepted when CE# is high.
SI (IO0),
SO (IO1)
INPUT/OUTPUT
Serial Data Input, Serial Output, and IOs (SI, SO, IO0, and IO1):
This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard SPI
instructions use the unidirectional SI (Serial Input) pin to write instructions, addresses,
or data to the device on the rising edge of the Serial Clock (SCK). Standard SPI also
uses the unidirectional SO (Serial Output) to read data or status from the device on
the falling edge of the serial clock (SCK).
In Dual and Quad SPI mode, SI and SO become bidirectional IO pins to write
instructions, addresses or data to the device on the rising edge of the Serial Clock
(SCK) and read data or status from the device on the falling edge of SCK. Quad SPI
instructions use the WP# and HOLD# pins as IO2 and IO3 respectively.
WP# (IO2)
INPUT/OUTPUT
Write Protect/Serial Data IO (IO2): The WP# pin protects the Status Register from
being written in conjunction with the SRWD bit. When the SRWD is set to “1” and the
WP# is pulled low, the Status Register bits (SRWD, QE, BP3, BP2, BP1, BP0) are
write-protected and vice-versa for WP# high. When the SRWD is set to “0”, the Status
Register is not write-protected regardless of WP# state.
When the QE bit is set to “1”, the WP# pin (Write Protect) function is not available
since this pin is used for IO2.
HOLD# (IO3)
INPUT/OUTPUT
Hold/Serial Data IO (IO3): Pauses serial communication by the master device
without resetting the serial sequence. When the QE bit of Status Register is set to
“1”, HOLD# pin is not available since it becomes IO3.
The HOLD# pin allows the device to be paused while it is selected. The HOLD# pin is
active low. When HOLD# is in a low state, and CE# is low, the SO pin will be at high
impedance.
Device operation can resume when HOLD# pin is brought to a high state. When the
QE bit of Status Register is set for Quad I/O, the HOLD# pin function is not available
and becomes IO3 for Multi-I/O SPI mode.
SCK
Vcc
GND
NC
INPUT
POWER
GROUND
Unused
Serial Data Clock: Synchronized Clock for input and output timing operations.
Power: Device Core Power Supply
Ground: Connect to ground when referenced to Vcc
NC: Pins labeled “NC” stand for “No Connect” and should be left uncommitted.
Integrated Silicon Solution, Inc.- www.issi.com
Rev.A
12/12/2014
6

6 Page



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部品番号部品説明メーカ
IS25LQ512B

3V QUAD SERIAL FLASH MEMORY

ISSI
ISSI


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