IS45VS16400L Datasheet PDF - Integrated Silicon Solution
| Part Number | IS45VS16400L | |
| Description | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM | |
| Manufacturers | Integrated Silicon Solution | |
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IS42VS16400L
IS45VS16400L
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
ADVANCED INFORMATION
APRIL 2012
FEATURES
• Clock frequency: 133 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single 1.8V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Self refresh modes
• Auto refresh (CBR)
• 4096 refresh cycles every 64 ms (Com, Ind, A1
grade) or 16ms (A2 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
OPTIONS
• Package:
54-ball TF-BGA (8mm x 8mm)
• Operating Temperature Range
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
Automotive Grade A1 (-40oC to +85oC)
Automotive Grade A2 (-40oC to +105oC)
OVERVIEW
ISSI's 64Mb Synchronous DRAM is organized as 1,048,576
bits x 16-bit x 4-bank for improved performance. The
synchronous DRAMs achieve high-speed data transfer
using pipeline architecture. All inputs and outputs signals
refer to the rising edge of the clock input.
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
-75 Unit
7.5 ns
10 ns
133 Mhz
100 Mhz
5.4 ns
8 ns
ADDRESS TABLE
Parameter
4M x 16
Configuration
1M x 16 x 4
banks
Refresh Count
Com./Ind.
A1
A2
4K/64ms
4K/64ms
4K/16ms
Row Addresses
A0-A11
Column Addresses
A0-A7
Bank Address Pins
BA0, BA1
Auto Precharge Pins
A10/AP
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
04/10/2012
1
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IS42VS16400L
IS45VS16400L
READ
The READ command selects the bank from BA0, BA1 inputs
and starts a burst read access to an active row. Inputs
A0-A7 provides the starting column location. When A10 is
HIGH, this command functions as an AUTO PRECHARGE
command. When the auto precharge is selected, the row
being accessed will be precharged at the end of the READ
burst. The row will remain open for subsequent accesses
when AUTO PRECHARGE is not selected. DQ’s read
data is subject to the logic level on the DQM inputs two
clocks earlier. When a given DQM signal was registered
HIGH, the corresponding DQ’s will be High-Z two clocks
later. DQ’s will provide valid data when the DQM signal
was registered LOW.
WRITE
A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank,
and the starting column location is provided by inputs
A0-A7. Whether or not AUTO-PRECHARGE is used is
determined by A10.
The row being accessed will be precharged at the end of
the WRITE burst, if AUTO PRECHARGE is selected. If
AUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses.
A memory array is written with corresponding input data
on DQ’s and DQM input logic level appearing at the same
time. Data will be written to memory when DQM signal is
LOW. When DQM is HIGH, the corresponding data inputs
will be ignored, and a WRITE will not be executed to that
byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open
row in a particular bank or the open row in all banks. BA0,
BA1 can be used to select which bank is precharged or they
are treated as “Don’t Care”. A10 determines whether one
or all banks are precharged.After executing this command,
the next command for the selected bank(s) is executed after
bpaansskapgreecohfathrgeinpge.r i oOdntcReP,
which is the period required for
a bank has been precharged, it
is in the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank.
AUTO PRECHARGE
The AUTO PRECHARGE function ensures that the
precharge is initiated at the earliest valid stage within a
burst. This function allows for individual-bank precharge
without requiring an explicit command. A10 can be used
to enable the AUTO PRECHARGE function in conjunc-
tion with a specific READ or WRITE command. For each
individual READ or WRITE command, auto precharge is
either enabled or disabled. AUTO PRECHARGE does not
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
04/10/2012
apply except in full-page burst mode. Upon completion of
the READ or WRITE burst, a precharge of the bank/row
that is addressed is automatically performed.
AUTO REFRESH COMMAND
This command executes the AUTO REFRESH operation.
The row address and bank to be refreshed are automatically
generatedduringthisoperation. Thestipulatedperiod(trc) is
required for a single refresh operation, and no other com-
mands can be executed during this period. This command
is executed at least 4096 times every Tref. During an AUTO
REFRESH command, address bits are “Don’t Care”. This
command corresponds to CBR Auto-refresh.
SELF REFRESH
During the SELF REFRESH operation, the row address to
be refreshed, the bank, and the refresh interval are gen-
erated automatically internally. SELF REFRESH can be
used to retain data in the SDRAM without external clocking,
even if the rest of the system is powered down. The SELF
REFRESH operation is started by dropping the CKE pin
from HIGH to LOW. During the SELF REFRESH operation
all other inputs to the SDRAM become “Don’t Care”. The
device must remain in self refresh mode for a minimum
period equal to tras or may remain in self refresh mode
for an indefinite period beyond that.The SELF-REFRESH
operation continues as long as the CKE pin remains LOW
and there is no need for external control of any other pins.
The next command cannot be executed until the device
internal recovery period (trc) has elapsed. Once CKE
goes HIGH, the NOP command must be issued (minimum
of two clocks) to provide time for the completion of any
internal refresh in progress. After the self-refresh, since it
is impossible to determine the address of the last row to
be refreshed, an AUTO-REFRESH should immediately be
performed for all addresses.
BURST TERMINATE
The BURST TERMINATE command forcibly terminates
the burst read and write operations by truncating either
fixed-length or full-page bursts and the most recently
registered READ or WRITE command prior to the BURST
TERMINATE.
COMMAND INHIBIT
COMMAND INHIBIT prevents new commands from being
executed. Operations in progress are not affected, apart
from whether the CLK signal is enabled
NO OPERATION
When CS is low, the NOP command prevents unwanted
commands from being registered during idle or wait
states.
5
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