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IS42VS16400L の電気的特性と機能

IS42VS16400LのメーカーはIntegrated Silicon Solutionです、この部品の機能は「1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS42VS16400L
部品説明 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS42VS16400L Datasheet, IS42VS16400L PDF,ピン配置, 機能
IS42VS16400L
IS45VS16400L
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
ADVANCED INFORMATION
APRIL 2012
FEATURES
• Clock frequency: 133 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single 1.8V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Self refresh modes
• Auto refresh (CBR)
• 4096 refresh cycles every 64 ms (Com, Ind, A1
grade) or 16ms (A2 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
OPTIONS
• Package:
54-ball TF-BGA (8mm x 8mm)
• Operating Temperature Range
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
Automotive Grade A1 (-40oC to +85oC)
Automotive Grade A2 (-40oC to +105oC)
OVERVIEW
ISSI's 64Mb Synchronous DRAM is organized as 1,048,576
bits x 16-bit x 4-bank for improved performance. The
synchronous DRAMs achieve high-speed data transfer
using pipeline architecture. All inputs and outputs signals
refer to the rising edge of the clock input.
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
-75 Unit
7.5 ns
10 ns
133 Mhz
100 Mhz
5.4 ns
8 ns
ADDRESS TABLE
Parameter
4M x 16
Configuration
1M x 16 x 4
banks
Refresh Count
Com./Ind.
A1
A2
4K/64ms
4K/64ms
4K/16ms
Row Addresses
A0-A11
Column Addresses
A0-A7
Bank Address Pins
BA0, BA1
Auto Precharge Pins
A10/AP
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
04/10/2012
1

1 Page





IS42VS16400L pdf, ピン配列
IS42VS16400L
IS45VS16400L
PIN CONFIGURATION
package code: B 54 bALL Tf-bga (Top View) (8 mm x 8 mm Body, 0.8 mm Ball Pitch)
123456789
A
GND DQ15 GNDQ
B
DQ14 DQ13 VDDQ
C
DQ12 DQ11 GNDQ
D
DQ10 DQ9 VDDQ
E
DQ8 NC GND
F
DQMH CLK CKE
G
NC A11 A9
H
A8 A7 A6
J
GND A5 A4
VDDQ DQ0 VDD
GNDQ DQ2 DQ1
VDDQ DQ4 DQ3
GNDQ DQ6 DQ5
VDD DQML DQ7
CAS RAS WE
BA0 BA1 CS
A0 A1 A10
A3 A2 VDD
PIN DESCRIPTIONS
A0-A11
Row Address Input
A0-A7
Column Address Input
BA0, BA1
Bank Select Addresses
DQ0 to DQ15 Data I/O
CLK
System Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe Command
CAS
Column Address Strobe Command
WE
Write Enable
LDQM, UDQM x16 Input/Output Mask
Vdd
Power
GND Ground
Vddq
Power Supply for I/O Pin
GNDQ Ground for I/O Pin
NC
No Connection
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  00A
04/10/2012
3


3Pages


IS42VS16400L 電子部品, 半導体
IS42VS16400L
IS45VS16400L
LOAD MODE REGISTER
During the LOAD MODE REGISTER command the mode
register is loaded from A0-A11. This command can only
be issued when all banks are idle.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1
inputs selects a bank to be accessed, and the address
inputs on A0-A11 selects the row. Until a PRECHARGE
command is issued to the bank, the row remains open
for accesses.
6 Integrated Silicon Solution, Inc. — www.issi.com
Rev.  00A
04/10/2012

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
IS42VS16400C1

1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

Integrated Silicon Solution
Integrated Silicon Solution
IS42VS16400E

1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

ISSI
ISSI
IS42VS16400L

1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

Integrated Silicon Solution
Integrated Silicon Solution


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