PDF IS43R16800CC Data sheet ( Hoja de datos )

Número de pieza	IS43R16800CC
Descripción	128Mb DDR Synchronous DRAM
Fabricantes	Integrated Silicon Solution
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IS43R16800CC 8Mx16 128Mb DDR Synchronous DRAM JUNE 2009 FEATURES: • Vdd =Vddq = 2.5V+0.2V (-5, -6, -75) • Double data rate architecture; two data transfers per clock cycle. • Bidirectional , data strobe (DQS) is transmitted/ received with data • Differential clock input (CLK and /CLK) • DLL aligns DQ and DQS transitions with CLK transitions edges of DQS • Commands entered on each positive CLK edge; • Data and data mask referenced to both edges of DQS • 4 bank operation controlled by BA0 , BA1 (Bank Address) • /CAS latency -2.0 / 2.5 / 3.0 (programmable) ; Burst length -2 / 4 / 8 (programmable) Burst type -Sequential / Interleave (program- mable) • Auto precharge/ All bank precharge controlled by A10 • 4096 refresh cycles / 64ms (4 banks concurrent refresh) • Auto refresh and Self refresh • Row address A0-11 / Column address A0-8 • SSTL_2 Interface • Package: 66-pin TSOP II • Temperature Range: Commercial (0oC to +70oC) Industrial (-40oC to +85oC) DESCRIPTION: IS43R16800CC is a 4-bank x 2,097,152-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The device achieves very high speed clock rate up to 200 MHz. KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2.5 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2.5 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2.5 CAS Latency = 2 -5 5 5 7.5 200 200 133 +0.70 +0.70 +0.75 -6 6 6 7.5 167 167 133 +0.70 +0.70 +0.75 -75 Unit 7.5 ns 7.5 ns 7.5 ns 133 MHz 133 MHz 133 MHz +0.75 ns +0.75 ns +0.75 ns ADDRESS TABLE Parameter 8M x 16 Configuration 2M x 16 x 4 banks Bank Address Pins BA0, BA1 Autoprecharge Pins A10/AP Row Addresses A0 – A11 Column Addresses A0 – A8 Refresh Count 4096 / 64ms Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. Rev. A 06/01/09 1 1 page ISI 43R16800CC Preliminary Zentel Electronics Corporation A3S56D30/40ETP 256M Double Data Rate Synchronous DRAM BASIC FUNCTIONS ISSI's 128-Mbit DDR SDRAM provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS , CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table. /CLK CLK /CS Chip Select : L=select, H=deselect /RAS Command /CAS Command define basic commands /WE Command CKE Refresh Option @refresh command A10 Precharge Option @precharge or read/write command Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates a row in an idle bank indicated by BA. Read (READ) [/RAS =H, /CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto- precharge, READA) Write (WRITE) [/RAS =H, /CAS =/WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA) Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read /write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA ). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H] REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically. IRDnetvDe. gRraSteDdRSAiliMcon(RSeovlu.1ti.o1n), Inc. 06/01/09 5 5 Page IS43R16800CC Preliminary Zentel Electronics Corporation A3S56D30/40ETP 256M Double Data Rate Synchronous DRAM FUNCTION TRUTH TABLE for CKE Current State CKE n-1 CKE n SELF- REFRESHING H L X H LH LH LH LH LL POWER H X DOWN LH LL ALL BANKS IDLE H H H L HL HL HL HL HL LX ANY STATE other than listed above H H L H L H LL /CS X H L L L L X X X X X L H L L L L X X X X X /RAS /CAS XX XX HH HH HL LX XX XX XX XX XX LL XX HH HH HL LX XX XX XX XX XX /WE Address Action Notes X X INVALID 1 X X Exit Self-Refresh (Idle after tRC) 1 H X Exit Self-Refresh (Idle after tRC) 1 L X ILLEGAL 1 X X ILLEGAL 1 X X ILLEGAL 1 X X NOP (Maintain Self-Refresh) 1 X X INVALID X X Exit Power Down to Idle X X NOP (Maintain Self-Refresh) X X Refer to Function Truth Table 2 H X Enter Self-Refresh 2 X X Enter Power Down 2 H X Enter Power Down 2 L X ILLEGAL 2 X X ILLEGAL 2 X X ILLEGAL 2 X X Refer to Current State =Power Down 2 X X Refer to Function Truth Table X X Begin CLK Suspend at Next Cycle 3 X X Exit CLK Suspend at Next Cycle 3 X X Maintain CLK Suspend ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command. Integrated Silicon Solution, Inc. DR06eD/v0.1 R/09SDRAM (Rev.1.1) 11 11 Page

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