DataSheet.jp

IS46R32400E の電気的特性と機能

IS46R32400EのメーカーはIntegrated Silicon Solutionです、この部品の機能は「128Mb DDR SDRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS46R32400E
部品説明 128Mb DDR SDRAM
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




このページの下部にプレビューとIS46R32400Eダウンロード(pdfファイル)リンクがあります。
Total 30 pages

No Preview Available !

IS46R32400E Datasheet, IS46R32400E PDF,ピン配置, 機能
IS43/46R16800E, IS43/46R32400E
4Mx32, 8Mx16 JANUARY 2014
128Mb DDR SDRAM
FEATURES
DEVICE OVERVIEW
• VDD and VDDQ: 2.5V ± 0.2V (-5,-6)
• VDD and VDDQ: 2.5V ± 0.1V (-4)
• SSTL_2 compatible I/O
• Double-data rate architecture; two data transfers
per clock cycle
• Bidirectional, data strobe (DQS) is transmitted/
received with data, to be used in capturing data
at the receiver
• DQS is edge-aligned with data for READs and
centre-aligned with data for WRITEs
• Differential clock inputs (CK and CK)
• DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Four internal banks for concurrent operation
• Data Mask for write data. DM masks write data
at both rising and falling edges of data strobe
• Burst Length: 2, 4 and 8
• Burst Type: Sequential and Interleave mode
• Programmable CAS latency: 2, 2.5, 3, and 4
• Auto Refresh and Self Refresh Modes
• Auto Precharge
• Tras Lockout supported (trap = trcd)
OPTIONS
• Configuration(s): 4Mx32, 8Mx16
• Package(s):
144 Ball BGA (x32)
66-pin TSOP-II (x16) and 60 Ball BGA (x16)
• Lead-free package available
• Temperature Range:
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Automotive, A1 (-40°C to +85°C)
Automotive, A2 (-40°C to +105°C)
ISSI’s 128-Mbit DDR SDRAM achieves high speed data
transfer using pipeline architecture and two data word
accesses per clock cycle. The 134,217,728-bit memory
array is internally organized as four banks of 32Mb to
allow concurrent operations. The pipeline allows Read
and Write burst accesses to be virtually continuous, with
the option to concatenate or truncate the bursts. The
programmable features of burst length, burst sequence
and CAS latency enable further advantages. The device
is available in 16-bit and 32-bit data word size Input
data is registered on the I/O pins on both edges of
Data Strobe signal(s), while output data is referenced
to both edges of Data Strobe and both edges of CLK.
Commands are registered on the positive edges of CLK.
An Auto Refresh mode is provided, along with a Self
Refresh mode. All I/Os are SSTL_2 compatible.
ADDRESS TABLE
Parameter
Configuration
Bank Address
Pins
Autoprecharge
Pins
Row Address
Column
Address
Refresh Count
Com./Ind./A1
A2
4M x 32
1M x 32 x 4
banks
BA0, BA1
A8/AP
4K(A0 – A11)
256(A0 – A7)
4K / 64ms
4K / 16ms
8M x 16
2M x 16 x 4
banks
BA0, BA1
A10/AP
4K(A0 – A11)
512(A0 – A8)
4K / 64ms
4K / 16ms
KEY TIMING PARAMETERS
Speed Grade
-4 -5 -6
Fck Max CL = 4
Fck Max CL = 3
Fck Max CL = 2.5
Fck Max CL = 2
250
200
——
200 167
167 167
133 133
Units
MHz
MHz
MHz
MHz
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest
version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. 1
Rev. C
1/16/14

1 Page





IS46R32400E pdf, ピン配列
IS43/46R16800E, IS43/46R32400E
FUNCTIONAL BLOCK DIAGRAM (x16)
CK
CK
CKE
CS
RAS
CAS
WE
COMMAND
DECODER
&
CLOCK
GENERATOR
Mode Registers and
Ext. Mode Registers
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
14
ROW
ADDRESS
12 LATCH
12
COLUMN
ADDRESS LATCH
9
BURST COUNTER
COLUMN
ADDRESS BUFFER
REFRESH
CONTROLLER
SELF
REFRESH
CONTROLLER
DATA IN
BUFFER
16
16
LDM, UDM
2
I/O 0-15
2 LDQS, UDQS
DATA OUT
BUFFER
16 16
VDD/VDDQ
Vss/VssQ
REFRESH
COUNTER
12
2
ROW
ADDRESS
BUFFER
12
12
4096
4096
4096
4096
MEMORY CELL
ARRAY
BANK 0
SENSE AMP I/O GATE
2 512
(x 16)
BANK CONTROL LOGIC
COLUMN DECODER
9
Integrated Silicon Solution, Inc.
Rev. C
1/16/14
3


3Pages


IS46R32400E 電子部品, 半導体
IS43/46R16800E, IS43/46R32400E
PIN CONFIGURATION
Package Code B: 144-ball FBGA (top view)
(12mm x 12mm Body, 0.8mm Ball Pitch)
Top View (Balls seen through the package)
1 2 3 4 5 6 7 8 9 10 11 12
A
B DQS0 DM0 VSSQ DQ3 DQ2 DQ0 DQ31 DQ29 DQ28 VSSQ DM3 DQS3
C DQ4 VDDQ NC VDDQ DQ1 VDDQ VDDQ DQ30 VDDQ NC VDDQ DQ27
D DQ6 DQ5 VSSQ VSSQ VSSQ VDD VDD VSSQ VSSQ VSSQ DQ26 DQ25
E DQ7 VDDQ VDD VSS VSSQ VSS VSS VSSQ VSS VDD VDDQ DQ24
F DQ17 DQ16 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ15 DQ14
G DQ19 DQ18 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ13 DQ12
H DQS2 DM2 NC VSSQ VSS VSS VSS VSS VSSQ NC DM1 DQS1
J DQ21 DQ20 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ11 DQ10
K DQ22 DQ23 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ9 DQ8
L CAS WE VDD VSS A10 VDD VDD NC VSS VDD NC NC
M RAS NC NC BA1 A2 A11 A9 A5 NC CK CK NC
CS NC BA0 A0 A1 A3 A4 A6 A7 A8 CKE VREF
Note: Vss balls inside the dotted box are optional for purposes of thermal dissipation.
PIN DESCRIPTION: for x32
A0-A11
A0-A7
BA0, BA1
DQ0 – DQ31
CK, CK
CKE
CS
CAS
RAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Column Address Strobe
Command
Row Address Strobe
Command
WE
DM0-DM3
DQS0-DQS3
VDD
VDDQ
VREF
VSS
VSSQ
NC
Write Enable
Data Write Mask
Data Strobe
Power
Power Supply for I/O Pins
SSTL_2 reference voltage
Ground
Ground for I/O Pins
No Connection
6 Integrated Silicon Solution, Inc.
Rev. C
1/16/14

6 Page



ページ 合計 : 30 ページ
 
PDF
ダウンロード
[ IS46R32400E データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
IS46R32400E

128Mb DDR SDRAM

Integrated Silicon Solution
Integrated Silicon Solution


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap