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PDF IS43R16800E Data sheet ( Hoja de datos )
| Número de pieza | IS43R16800E | |
| Descripción | 128Mb DDR SDRAM | |
| Fabricantes | Integrated Silicon Solution | |
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IS43/46R16800E, IS43/46R32400E
4Mx32, 8Mx16 JANUARY 2014
128Mb DDR SDRAM
FEATURES
DEVICE OVERVIEW
• VDD and VDDQ: 2.5V ± 0.2V (-5,-6)
• VDD and VDDQ: 2.5V ± 0.1V (-4)
• SSTL_2 compatible I/O
• Double-data rate architecture; two data transfers
per clock cycle
• Bidirectional, data strobe (DQS) is transmitted/
received with data, to be used in capturing data
at the receiver
• DQS is edge-aligned with data for READs and
centre-aligned with data for WRITEs
• Differential clock inputs (CK and CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Four internal banks for concurrent operation
• Data Mask for write data. DM masks write data
at both rising and falling edges of data strobe
• Burst Length: 2, 4 and 8
• Burst Type: Sequential and Interleave mode
• Programmable CAS latency: 2, 2.5, 3, and 4
• Auto Refresh and Self Refresh Modes
• Auto Precharge
• Tras Lockout supported (trap = trcd)
OPTIONS
• Configuration(s): 4Mx32, 8Mx16
• Package(s):
144 Ball BGA (x32)
66-pin TSOP-II (x16) and 60 Ball BGA (x16)
• Lead-free package available
• Temperature Range:
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Automotive, A1 (-40°C to +85°C)
Automotive, A2 (-40°C to +105°C)
ISSI’s 128-Mbit DDR SDRAM achieves high speed data
transfer using pipeline architecture and two data word
accesses per clock cycle. The 134,217,728-bit memory
array is internally organized as four banks of 32Mb to
allow concurrent operations. The pipeline allows Read
and Write burst accesses to be virtually continuous, with
the option to concatenate or truncate the bursts. The
programmable features of burst length, burst sequence
and CAS latency enable further advantages. The device
is available in 16-bit and 32-bit data word size Input
data is registered on the I/O pins on both edges of
Data Strobe signal(s), while output data is referenced
to both edges of Data Strobe and both edges of CLK.
Commands are registered on the positive edges of CLK.
An Auto Refresh mode is provided, along with a Self
Refresh mode. All I/Os are SSTL_2 compatible.
ADDRESS TABLE
Parameter
Configuration
Bank Address
Pins
Autoprecharge
Pins
Row Address
Column
Address
Refresh Count
Com./Ind./A1
A2
4M x 32
1M x 32 x 4
banks
BA0, BA1
A8/AP
4K(A0 – A11)
256(A0 – A7)
4K / 64ms
4K / 16ms
8M x 16
2M x 16 x 4
banks
BA0, BA1
A10/AP
4K(A0 – A11)
512(A0 – A8)
4K / 64ms
4K / 16ms
KEY TIMING PARAMETERS
Speed Grade
-4 -5 -6
Fck Max CL = 4
Fck Max CL = 3
Fck Max CL = 2.5
Fck Max CL = 2
250
200
—
—
——
200 167
167 167
133 133
Units
MHz
MHz
MHz
MHz
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest
version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. 1
Rev. C
1/16/14
1 page  
IS43/46R16800E, IS43/46R32400E
PIN CONFIGURATION
Package Code B: 60-ball FBGA (top view) for x16
(8mm x 13mm Body, 0.8mm Ball Pitch)
Top View
(Balls seen through the Package)
: Ball Existing
: Depopulated Ball
Top View(See the balls through the Package)
1 23456789
A
B
C
D
E
F
G
H
J
K
L
M
BGA Package Ball Pattern
Top View
1 23
78
9
VSSQ DQ15 VSS A VDD DQ0 VDDQ
DQ14 VDDQ DQ13 B DQ2 VSSQ DQ1
DQ12 VSSQ DQ11 C DQ4 VDDQ DQ3
DQ10 VDDQ DQ9 D DQ6 VSSQ DQ5
DQ8 VSSQ UDQS
VREF VSS UDM
E
F
LDQS VDDQ DQ7
LDM VDD NC
CK CK G WE CAS
NC CKE H RAS CS
A11 A9 J BA1 BA0
A8 A7 K A0 A10/AP
A6 A5 L A2 A1
A4 VSS M VDD A3
x 16 Device Ball Pattern
PIN DESCRIPTION: x16
A0-A11
A0-A8
BA0, BA1
DQ0 – DQ15
CK, CK
CKE
CS
CAS
RAS
WE
LDM, UDM
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Column Address Strobe
Command
Row Address Strobe Command
Write Enable
Data Write Mask
Integrated Silicon Solution, Inc.
Rev. C
1/16/14
LDQS, UDQS
VDD
VDDQ
VSS
VSSQ
VREF
NC
Data Strobe
Power
Power Supply for I/O Pins
Ground
Ground for I/O Pins
SSTL_2 reference voltage
No Connection
5
5 Page 
IS43/46R16800E, IS43/46R32400E
FUNCTIONAL DESCRIPTION
The DDR SDRAM is a high speed CMOS, dynamic random-access memory internally configured as a quad-bank
DRAM. The 128Mb devices contains: 134,217,728 bits.
The DDR SDRAM uses double data rate architecture to achieve high speed operation. The double data rate
architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock
cycle at the I/O pins. A single read or write access for the DDR SDRAM effectively consists of a single 2n-bit wide,
one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle
data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The
address bits registered coincident with the READ or WRITE command are used to select the bank and the starting
column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized. The following section provides detailed information
covering device initialization, register definition, command description and device operation
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner. Operations procedures other than those
specified may result in undefined operation. If there is any interruption to the device power, the initialization routine
should be followed. The steps to be followed for device initialization are listed below. The Initialization Flow diagram
and the Initialization Flow sequence are shown in the following figures.
The Mode Register and Extended Mode Register do not have default values. If they are not programmed during the
initialization sequence, it may lead to unspecified operation. The clock stop feature is not available until the device has
been properly initialized from Step 1 through 13.
• Step 1: Apply VDD before or at the same time as VDDQ.
• Step 2: CKE must maintain LVCMOS Low until VREF is stable. Apply VDDQ before applying VTT and VREF.
• Step 3: There must be at least 200 μs of valid clocks before any command may be given to the DRAM. During this
time NOP or DESELECT commands must be issued on the command bus and CKE should be brought HIGH.
• Step 4: Issue a PRECHARGE ALL command.
• Step 5: Provide NOPs or DESELECT commands for at least tRP time.
• Step 6: Issue EMRS command
• Step 7: Issue MRS command, load the base mode register and to reset the DLL. Set the desired operating modes.
• Step 8: Provide NOPs or DESELECT commands for at least tMRD time.
• Step 9: Issue a PRECHARGE ALL command
• Step 10: Issue 2 or more AUTO REFRESH cycles
• Step 11: Issue MRS command with the reset DLL bit deactivated to program operating parameters without resetting
the DLL
• Step 12: Provide NOP or DESELECT commands for at least tMRD time.
• Step 13: The DRAM has been properly initialized and is ready for any valid command.
Integrated Silicon Solution, Inc. 11
Rev. C
1/16/14
11 Page | ||
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| PDF Descargar | [ Datasheet IS43R16800E.PDF ] | |
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