PDF IS43R32800 Data sheet ( Hoja de datos )

Número de pieza	IS43R32800
Descripción	256Mb DDR Synchronous DRAM
Fabricantes	Integrated Silicon Solution
Logotipo
Hay una vista previa y un enlace de descarga de IS43R32800 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! IS43R32800 8Mx32 256Mb DDR Synchronous DRAM FEBUARY 2009 FEATURES • Vdd/Vddq=2.5V+0.2V (-5, -6, -75) • Double data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data • Differential clock input (CLK and /CLK) • DLL aligns DQ and DQS transitions with CLK transitions edges of DQS • Commands entered on each positive CLK edge; • Data and data mask referenced to both edges of DQS • 4 bank operation controlled by BA0, BA1 (Bank Address) • /CAS latency –2.0/2.5/3.0 (programmable) • Burst length - 2/4/8 (programmable) • Burst type - Sequential/ Interleave (program- mable) • Auto precharge / All bank precharge controlled by A8 • 4096 refresh cycles/ 64ms (4 banks concurrent refresh) • Auto refresh and Self refresh • Row address A0-11/ Column address A0-7, A9- SSTL_2 Interface • Package 144-ball FBGA • Available in Industrial Temperature • Temperature Range: Commercial (0oC to +70oC) DESCRIPTION: IS43R32800 is a 4-bank x 2,097,152-word x32bit Double Data Rate Synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The IS43R32800 achieves very high speed clock rate up to 200 MHz . It is packaged in 144-ball FBGA. KEY TIMING PARAMETERS Parameter -5 -6 -75 Unit Clk Cycle Time CAS Latency = 3 5 6 7.5 ns CAS Latency = 2.5 5 6 7.5 ns CAS Latency = 2 7.5 7.5 7.5 ns Clk Frequency CAS Latency = 3 200 167 143 MHz CAS Latency = 2.5 200 167 143 MHz CAS Latency = 2 143 143 143 MHz Access Time from Clock CAS Latency = 3 +0.70 +0.70 +0.70 ns CAS Latency = 2.5 +0.70 +0.70 +0.70 ns CAS Latency = 2 +0.75 +0.75 +0.70 ns ADDRESS TABLE Parameter 8M x 32 Configuration 2M x 32 x 4 banks Bank Address Pins BA0, BA1 Autoprecharge Pins A8/AP Row Addresses A0 – A11 Column Addresses A0 – A7, A9 Refresh Count 4096 / 64ms Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 1 1 page IS43R32800 FUNCTIONAL DESCRIPTION ISSI's 256-Mbit DDR SDRAM provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. E ach command is defined by control signals of /RA S, /CAS and /WE at CLK rising edge. I n addition to 3 signals, /CS ,C KE and A8 are usedas chip select, refresh option, and prechargeoption, respectively. To know the detailed definition of commands, please see the command truth table. /CLK CL K /CS Chip Select : L =select, H=deselect /RAS Command /CAS Command define basic commands /WE Command CK E Refresh Option @ refresh command A8 Precharge Option @ precharge or read/write command Activate ( ACT) [/RA S =L, /CAS =/WE =H ] AC T c ommand activates a row in an idle bank indicated by BA . Read (R EAD) [/RAS =H , /CA S =L, /WE = H] RE AD command starts burst read from the active bank indicated by BA . F irst output data appears after /CAS latency. When A8 =H at this command, the bank is deactivated after the burst read (auto- precharge READ A ) Write (WRITE) [/RA S =H, /CAS =/WE =L ] WR IT E c ommand starts burst write to the active bank indicated by BA . T otal data length to be written is set by burst length. W hen A8 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA ) Prechar ge (P RE ) [ /RAS =L , /CA S =H, /WE = L] PR E c ommand deactivates the active bank indicated by BA . T his command also terminates burst read /write operation. When A8 =H at this command, all banks are deactivated (precharge all, PREA ). Auto-Ref resh (REFA ) [ /RAS =/CA S =L, /WE = CK E = H] RE FA command starts auto-refresh cycle. R efresh address including bank address are generated internally. A fter this command, the banks are precharged automatically. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 5 5 Page IS43R32800 CKE TRUTH TABLE Current State CKE n-1 CKE n /CS SELF - HXX REFR ESHI NG L H H LHL LHL LHL LHL LLX POWER DO WN HXX L HX LLX ALL BANKS H H X IDLE H L L HLH HLL HLL HLL HLL LXX H HX ANY STATE other than listed H L X above L HX LLX /RAS /CAS XX XX HH HH HL LX XX XX XX XX XX LL XX HH HH HL LX XX XX XX XX XX /WE Address A ction N otes X X I NV ALID 1 X X Exit Self-Refresh (Idle after tRC ) 1 H X Exit Self-Refresh (Idle after tRC ) 1 L X I LL EGAL 1 X X I LL EGAL 1 X X I LL EGAL 1 X X N OP (M aintain Self- Refresh) 1 X X I NV AL ID X X Exit Power Downto Idle X X N OP (M aintain Self- Refresh) X X R efer to FunctionTruth Table 2 H X Enter Self-R efresh 2 X X Enter Power Down 2 H X Enter Power Down 2 L X I LL EGAL 2 X X I LL EGAL 2 X X I LL EG AL 2 X X R efer to Current State =Power Down 2 X X R efer to FunctionTruth Table X X B egin CL K S uspend at Next Cycle 3 X X Exit CLK Suspend at Next Cycle 3 X X M aintain CLK Suspend ABBR EVIATI ONS : H=Hi gh Level, L= Low L evel, X =Don't Care NOTES : 1. CKE L ow to Hi gh transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the Al l B anks Idle State. 3. Must be legal command. Integrated Silicon Solution, Inc. — www.issi.com Rev. 01/14/09 11 11 Page

Páginas	Total 30 Páginas
PDF Descargar	[ Datasheet IS43R32800.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
IS43R32800	256Mb DDR Synchronous DRAM	Integrated Silicon Solution
IS43R32800B	256Mb DDR Synchronous DRAM PRELIMINARY INFORMATION	Integrated Silicon Solution
IS43R32800D	DDR SDRAM	ISSI
IS43R32800D	DDR SDRAM	ISSI

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar