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PDF IS61C6416 Data sheet ( Hoja de datos )
| Número de pieza | IS61C6416 | |
| Descripción | 64K x 16 HIGH-SPEED CMOS STATIC RAM | |
| Fabricantes | Integrated Silicon Solution | |
| Logotipo |  |
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IS61C6416
64K x 16 HIGH-SPEED CMOS STATIC RAM
ISSI®
MAY 1999
FEATURES
• High-speed access time: 10, 12, 15, and 20 ns
• CMOS low power operation
— 1650 mW (max) @ -10ns Cycle
— 55 µW (max) CMOS Standby
• TTL compatible interface levels
• Single 5V ± 10% power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial temperature available
• Available in 44-pin SOJ package and
44-pin TSOP (Type II)
DESCRIPTION
The ISSI IS61C6416 is a high-speed, 1,048,576-bit static
RAM organized as 65,536 words by 16 bits. It is fabricated
using ISSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design tech-
niques, yields access times as fast as 10 ns with low power
consumption.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down
with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.A
data byte allows Upper Byte (UB) and Lower Byte (LB) access.
The IS61C6416 is packaged in the JEDEC standard 44-pin
400-mil SOJ and 44-pin TSOP (Type II).
FUNCTIONAL BLOCK DIAGRAM
A0-A15
DECODER
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
CE
OE CONTROL
WE CIRCUIT
UB
LB
64K x 16
MEMORY ARRAY
COLUMN I/O
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR005-1D
05/24/99
1
1 page  
IS61C6416
ISSI®
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
t RC
ADDRESS
DOUT
PREVIOUS DATA VALID
t OHA
t AA
t OHA
DATA VALID
1
2
READ1.eps
3
READ CYCLE NO. 2(1,3)
ADDRESS
OE
CE
LB, UB
t LZCE
DOUT
t LZB
HIGH-Z
t RC
t AA
t DOE
t LZOE
t ACE
t BA
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
4
t HZCE
DATA VALID
t OHA
t HZOE
5
6
7
t HZB
8
UB_CEDR2.eps
9
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR005-1D
05/24/99
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet IS61C6416.PDF ] | |
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