PDF IS61C1024L Data sheet ( Hoja de datos )

Número de pieza	IS61C1024L
Descripción	128K x 8 HIGH-SPEED CMOS STATIC RAM
Fabricantes	Integrated Silicon Solution
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No Preview Available ! IS61C1024 IS61C1024L 128K x 8 HIGH-SPEED CMOS STATIC RAM ISSI® MAY 1999 FEATURES • High-speed access time: 12, 15, 20, 25 ns • Low active power: 600 mW (typical) • Low standby power: 500 µW (typical) CMOS standby • Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single 5V (±10%) power supply • Low power version available: IS61C1024L • Commercial and industrial temperature ranges available DESCRIPTION The ISSI IS61C1024 and IS61C1024L are very high-speed, low power, 131,072-word by 8-bit CMOS static RAMs. They are fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61C1024 and IS61C1024L are available in 32-pin 300-mil SOJ, and TSOP (Type I, 8x20), and sTSOP (Type I, 8 x 13.4) packages. FUNCTIONAL BLOCK DIAGRAM A0-A16 VCC GND I/O0-I/O7 DECODER I/O DATA CIRCUIT 512 x 2048 MEMORY ARRAY COLUMN I/O CE1 CE2 CONTROL OE CIRCUIT WE ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. — 1-800-379-4774 SR028-1K 05/12/99 1 1 page IS61C1024 IS61C1024L ISSI® READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter -12(2) Min. Max. -15 ns Min. Max. -20 ns Min. Max. -25 ns Min. Max. Unit tRC Read Cycle Time 12 — 15 — 20 — 25 — ns tAA Address Access Time — 12 — 15 — 20 — 25 ns tOHA Output Hold Time 3— 3— 3— 3— ns tACE1 CE1 Access Time — 12 — 15 — 20 — 25 ns tACE2 CE2 Access Time — 12 — 15 — 20 — 25 ns tDOE OE Access Time —6 —7 —9 —9 ns tLZOE(3) OE to Low-Z Output 0— 0— 0— 0— ns tHZOE(3) OE to High-Z Output 06 06 07 0 10 ns tLZCE1(3) CE1 to Low-Z Output 2— 2— 3— 3— ns tLZCE2(3) CE2 to Low-Z Output 2— 2— 3— 3— ns tHZCE(3) CE1 or CE2 to High-Z Output 07 08 09 0 10 ns tPU(4) CE1 or CE2 to Power-Up 0— 0— 0— 0— ns tPD(4) CE1 or CE2 to Power-Down — 12 — 12 — 18 — 20 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. -12 ns device for IS61C1024 only. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 4. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 480 Ω 5V 480 Ω 5V OUTPUT OUTPUT 30 pF Including jig and scope Figure 1 255 Ω 5 pF Including jig and scope Figure 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 SR028-1K 05/12/99 255 Ω 5 5 Page IS61C1024 IS61C1024L ISSI® Integrated Silicon Solution, Inc. — 1-800-379-4774 SR028-1K 05/12/99 ISSI® Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: [email protected] www.issi.com 11 11 Page

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Número de pieza	Descripción	Fabricantes
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