IS61DDPB42M36A1 Datasheet PDF - Integrated Silicon Solution
| Part Number | IS61DDPB42M36A1 | |
| Description | 72Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM | |
| Manufacturers | Integrated Silicon Solution | |
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IS61DDPB44M18A/A1/A2
IS61DDPB42M36A/A1/A2
4Mx18, 2Mx36
72Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM
(2.5 Cycle Read Latency)
ADVANCED INFORMATION
JULY 2012
FEATURES
DESCRIPTION
2Mx36 and 4Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data
valid window.
Common I/O read and write ports.
Synchronous pipeline read with self-timed late write
operation.
Double Data Rate (DDR) interface for read and
write input ports.
2.5 cycle read latency.
Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control
registering at rising edges only.
Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data.
+1.8V core power supply and 1.5V to 1.8V VDDQ,
used with 0.75 to 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte
writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1
functions.
Byte write capability.
Fine ball grid array (FBGA) package:
13mm x 15mm & 15mm x 17mm body size
165-ball (11 x 15) array
Programmable impedance output drivers via 5x
user-supplied precision resistor.
Data Valid Pin (QVLD).
ODT (On Die Termination) feature is supported
optionally on data inputs, K/K#, and BWx#.
The end of top mark (A/A1/A2) is to define options.
IS61DDPB42M36A : Don’t care ODT function
and pin connection
IS61DDPB42M36A1 : Option1
IS61DDPB42M36A2 : Option2
Refer to more detail description at page 6 for each
ODT option.
The 72Mb IS61DDPB42M36A/A1/A2 and
IS61DDPB44M18A/A1/A2 are synchronous, high-
performance CMOS static random access memory (SRAM)
devices. These SRAMs have a common I/O bus. The rising
edge of K clock initiates the read/write operation, and all
internal operations are self-timed. Refer to the Timing
Reference Diagram for Truth Table for a description of the
basic operations of these DDR-IIP (Burst of 4) CIO SRAMs.
Read and write addresses are registered on alternating rising
edges of the K clock. Reads and writes are performed in
double data rate.
The following are registered internally on the rising edge of
the K clock:
Read/write address
Read enable
Write enable
Byte writes
Data-in for first and third burst addresses
Data-out for second and fourth burst addresses
The following are registered on the rising edge of the K#
clock:
Byte writes
Data-in for second and fourth burst addresses
Data-out for first and third burst addresses
Byte writes can change with the corresponding data-in to
enable or disable writes on a per-byte basis. An internal write
buffer enables the data-ins to be registered one cycle after
the write address. The first data-in burst is clocked one cycle
later than the write command signal, and the second burst is
timed to the following rising edge of the K# clock. Two full
clock cycles are required to complete a write operation.
During the burst read operation, the data-outs from the first
bursts are updated from output registers of the third rising
edge of the K# clock (starting two and half cycles later after
read command). The data-outs from the second burst are
updated with the fourth rising edge of the K clock where read
command receives at the first rising edge of K.
The device is operated with a single +1.8V power supply and
is compatible with HSTL I/O interfaces.
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
7/05/2012
1
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IS61DDPB44M18A/A1/A2
IS61DDPB42M36A/A1/A2
The data-in provided for writing is initially kept in write buffers. The information on these buffers is written into the array
on the third write cycle. A read cycle to the last two write address produces data from the write buffers. Similarly, a
read address followed by the same write address produces the latest write data. The SRAM maintains data coherency.
During a write, the byte writes independently control which byte of any of the two burst addresses is written. (See
X18/X36 Write Truth Tables and Timing Reference Diagram for Truth Table)
Whenever a write is disabled (R/W# is high at the rising edge of K), data is not written into the memory.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust
its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the
SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range of RQ to guarantee
impedance matching is between 175Ω and 350Ω at VDDQ=1.5V. The RQ resistor should be placed less than two inches
away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 7.5pF.
The ZQ pin can also be directly connected to VDDQ to obtain a minimum impedance setting. ZQ should not be
connected to VSS.
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in
supply voltage and temperature. During power-up, the driver impedance is in the middle of allowable impedances
values. The final impedance value is achieved within 1024clock cycles.
Valid Data Indicator (QVLD)
A data valid pin (QVLD) is available to assist in high-speed data output capture. This output signal is edge-aligned with
the echo clock and is asserted HIGH half a cycle before valid read data is available and asserted LOW half a cycle
before the final valid read data arrives.
Delay Locked Loop (DLL)
Delay Locked Loop (DLL) is a new system to align the output data coincident with clock rising or falling edge to
enhance the output valid timing characteristics. It is locked to the clock frequency and is constantly adjusted to match
the clock frequency. Therefore device can have stable output over the temperature and voltage variation.
DLL has a limitation of locking range and jitter adjustment which are specified as tKHKH and tKCvar respectively in the
AC timing characteristics. In order to turn this feature off, applying logic low to the Doff# pin will bypass this. In the DLL
off mode, the device behaves with one cycle latency and a longer access time which is known in DDR-I or legacy
QUAD mode.
The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K#
for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is
not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being
reset, it gets locked after 2048 cycles of stable clock.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
7/05/2012
5
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ IS61DDPB42M36A1.PDF Datasheet ] | |
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