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IS61DDPB24M18 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 IS61DDPB24M18
部品説明 DDR-IIP (Burst of 2) CIO Synchronous SRAMs
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 



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IS61DDPB24M18 Datasheet, IS61DDPB24M18 PDF,ピン配置, 機能
72 Mb (2M x 36 & 4M x 18)
DDR-IIP (Burs. t of 2) CIO Synchronous SRAMs
(2.5 Cycle Read Latency)
Advanced Information
May 2009
Features
2M x 36 or 4M x 18.
• On-chip delay-locked loop (DLL) for wide data
valid window.
• Common data input/output bus.
Synchronous pipeline read with self-timed late
write operation.
• Double data rate (DDR-IIP) interface for read and
write input ports.
• Fixed 2-bit burst for read and write operations.
• Clock stop support.
• Two input clocks (K and K) for address and con-
trol registering at rising edges only.
Industrial temperature available upon request.
Two echo clocks (CQ and CQ) that are delivered
simultaneously with data.
• +1.8V core power supply and 1.5, 1.8V VDDQ,
used with 0.75, 0.9V VREF.
HSTL input and output levels.
• Registered addresses, write and read controls,
byte writes, data in, and data outputs.
• Full data coherency.
• Boundary scan using limited set of JTAG 1149.1
functions.
Byte write capability.
• Fine ball grid array (FBGA) package
- 15mm x 17mm body size
- 1mm pitch
- 165-ball (11 x 15) array
• Programmable impedance output drivers via 5x
user-supplied precision resistor.
Description
The 72Mb IS61DDPB22M36 and
IS61DDPB24M18 are synchronous, high-perfor-
mance CMOS static random access memory
(SRAM) devices. These SRAMs have a common I/O
bus. The rising edge of K clock initiates the
read/write operation, and all internal operations are
self-timed.
Refer to the Timing Reference Diagram for Truth
Table on page 8 for a description of the basic opera-
tions of these DDR-IIP (Burst of 2) CIO SRAMs.
The input addresses are registered on all rising
edges of the K clock. The DQ bus operates at
double data rate for reads and writes. The following
are registered internally on the rising edge of the K
clock:
Read and write addresses
Address load
• Read/write enable
Byte writes
• Data-in
Data-out
The following are registered on the rising edge of
the K clock:
Byte writes
• Data-in for second burst addresses
Data-out
Byte writes can change with the corresponding data-
in to enable or disable writes on a per-byte basis. An
internal write buffer enables the data-ins to be regis-
tered one cycle later than the write address. The first
data-in burst is clocked with the rising edge of the
next K clock, and the second burst is timed to the
following rising edge of the K clock.
During the burst read operation, at the first burst the
data-outs are updated from output registers off the
second rising edge of the K clock (2.5 cycles later).
At the second burst, the data-outs are updated with
the fourth rising edge of the corresponding K clock
(see page 8).
The device is operated with a single +1.8V power
supply and is compatible with HSTL I/O interfaces.
Integrated Silicon Solution, Inc.
Rev.  00A
03/31/08
1

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