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IS61DDPB24M18のメーカーはIntegrated Silicon Solutionです、この部品の機能は「DDR-IIP (Burst of 2) CIO Synchronous SRAMs」です。 |
部品番号 | IS61DDPB24M18 |
| |
部品説明 | DDR-IIP (Burst of 2) CIO Synchronous SRAMs | ||
メーカ | Integrated Silicon Solution | ||
ロゴ | |||
このページの下部にプレビューとIS61DDPB24M18ダウンロード(pdfファイル)リンクがあります。 Total 24 pages
72 Mb (2M x 36 & 4M x 18)
DDR-IIP (Burs. t of 2) CIO Synchronous SRAMs
(2.5 Cycle Read Latency)
Advanced Information
May 2009
Features
• 2M x 36 or 4M x 18.
• On-chip delay-locked loop (DLL) for wide data
valid window.
• Common data input/output bus.
• Synchronous pipeline read with self-timed late
write operation.
• Double data rate (DDR-IIP) interface for read and
write input ports.
• Fixed 2-bit burst for read and write operations.
• Clock stop support.
• Two input clocks (K and K) for address and con-
trol registering at rising edges only.
• Industrial temperature available upon request.
• Two echo clocks (CQ and CQ) that are delivered
simultaneously with data.
• +1.8V core power supply and 1.5, 1.8V VDDQ,
used with 0.75, 0.9V VREF.
• HSTL input and output levels.
• Registered addresses, write and read controls,
byte writes, data in, and data outputs.
• Full data coherency.
• Boundary scan using limited set of JTAG 1149.1
functions.
• Byte write capability.
• Fine ball grid array (FBGA) package
- 15mm x 17mm body size
- 1mm pitch
- 165-ball (11 x 15) array
• Programmable impedance output drivers via 5x
user-supplied precision resistor.
Description
The 72Mb IS61DDPB22M36 and
IS61DDPB24M18 are synchronous, high-perfor-
mance CMOS static random access memory
(SRAM) devices. These SRAMs have a common I/O
bus. The rising edge of K clock initiates the
read/write operation, and all internal operations are
self-timed.
Refer to the Timing Reference Diagram for Truth
Table on page 8 for a description of the basic opera-
tions of these DDR-IIP (Burst of 2) CIO SRAMs.
The input addresses are registered on all rising
edges of the K clock. The DQ bus operates at
double data rate for reads and writes. The following
are registered internally on the rising edge of the K
clock:
• Read and write addresses
• Address load
• Read/write enable
Byte writes
• Data-in
• Data-out
The following are registered on the rising edge of
the K clock:
• Byte writes
• Data-in for second burst addresses
• Data-out
Byte writes can change with the corresponding data-
in to enable or disable writes on a per-byte basis. An
internal write buffer enables the data-ins to be regis-
tered one cycle later than the write address. The first
data-in burst is clocked with the rising edge of the
next K clock, and the second burst is timed to the
following rising edge of the K clock.
During the burst read operation, at the first burst the
data-outs are updated from output registers off the
second rising edge of the K clock (2.5 cycles later).
At the second burst, the data-outs are updated with
the fourth rising edge of the corresponding K clock
(see page 8).
The device is operated with a single +1.8V power
supply and is compatible with HSTL I/O interfaces.
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
1
1 Page ID72DMb (2M x 36 & 4M x 18)
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
3
Pin Description
Symbol
Pin Number
Description
K, K
CQ, CQ
Doff
6B, 6A
11A, 1A
1H
Input clock.
Output echo clock.
DLL disable when low.
SA
3A, 9A, 10A, 4B, 8B, 5C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R,
5R, 7R,8R, 9R
2M x 36 address inputs.
SA
2A, 3A, 9A, 10A, 4B, 8B, 5C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R,
4R, 5R, 7R, 8R, 9R
4M x 18 address inputs.
DQ0–DQ8
DQ9–DQ17
DQ18–DQ26
DQ27–DQ35
11P, 11M, 11L, 11K, 11J, 11F, 11E, 11C, 11B
10P, 11N, 10M, 10K, 10J, 11G, 10E, 11D, 10C
3B, 3D, 3E, 3F, 3G, 3K, 3L, 3N, 3P
2B, 3C, 2D, 2F, 2G, 3J, 2L, 3M, 2N
2M x 36 DQ pins
DQ0–DQ8
DQ9–DQ17
11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B
2B, 3D, 3E, 2F, 3G, 3K, 2L, 3N, 3P
4M x 18 DQ pins
R/W 4A
Read/write control. Read when active high.
LD 8A
Synchronizes load. Loads new address
when low.
BW0, BW1, BW2, BW3 7B, 7A, 5A,5B
BW0, BW1
7B, 5A
VREF
2H, 10H
VDD 5F, 7F, 5G, 7G, 5H, 7H, 5J, 7J, 5K, 7K
VDDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
VSS
4C, 8C, 4D, 5D, 6D, 7D, 8D, 5E, 6E, 7E, 6F, 6G, 6H, 6J,
6K, 5L, 6L, 7L, 4M, 5M, 6M, 7M, 8M, 4N, 8N
2M x 36 byte write control, active low.
4M x 18 byte write control, active low.
Input reference level.
Power supply.
Output power supply.
Ground
ZQ 11H
Output driver impedance control.
TMS, TDI, TCK
10R, 11R, 2R
IEEE 1149.1 test inputs (1.8V LVTTL lev-
els).
TDO
1R
IEEE 1149.1 test output (1.8V LVTTL level).
NC 2A, 1B, 9B, 10B, 1C, 2C, 9C, 1D, 9D, 10D, 1E, 2E, 9E, 1F, 9F, x36 Configuration
10F, 1G, 9G, 10G, 1J, 2J, 9J, 1K, 2K, 9K, 1L, 9L, 10L, 1M, 2M,
9M, 1N, 9N, 10N, 1P, 2P, 9P, 6R, 6P, 6C
NC
7A, 1B, 3B, 5B, 9B, 10B, 1C, 2C, 3C, 9C, 11C, 1D, 2D, 9D, 10D, x18 Configuration
11D, 1E, 2E, 9E, 10E, 1F, 3F, 9F, 10F, 1G, 2G, 9G, 10G, 11G,
1J, 2J, 3J, 9J, 11J, 1K, 2K, 9K, 10K, 1L, 3L, 9L, 10L, 1M, 2M, 3M,
9M, 11M, 1N, 2N, 9N, 10N, 11N, 1P, 2P, 9P, 10P, 6R, 6P, 6C
Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
3
3Pages 72 Mb (2M x 36 & 4M x 18)
DDR-IIP (Burst of 2) CIO Synchronous SRAMs
Application Example
The following figure depicts an implementation of four 4M x 18 DDR-IIP SRAMs with common I/Os.
SRAM #1
Data-In/Data-Out
Echo Clock
Echo Clock
Address
Vt
R
LD
R/W
Memory
Controller
BW
SA LD R/W BW0 BW1
Source CLK
Source CLK
R=50 Vt=VREF
ZQ R=250
CQ/CQ
DQ0–17
KK
SRAM #4
SA LD R/W BW0 BW1
ZQ R=250
CQ/CQ
DQ0–17
KK
Vt
R
Power-Up and Power-Down Sequences
The following sequence is used for power-up:
1. The power supply inputs must be applied in the following order while keeping Doff in LOW logic state:
1) VDD
2) VDDQ
3) VREF
2. Start applying stable clock inputs (K, K, C, and C).
3. After clock signals have stabilized, change Doff to HIGH logic state.
4. Once the Doff is switched to HIGH logic state, wait an additional 1024 clock cycles to lock the DLL.
NOTES:
1. The power-down sequence must be done in reverse of the power-up sequence.
2. VDDQ can be allowed to exceed VDD by no more than 0.6V.
3. VREF can be applied concurrently with VDDQ.
6 Integrated Silicon Solution, Inc.
Rev. 00A
03/31/08
6 Page | |||
ページ | 合計 : 24 ページ | ||
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部品番号 | 部品説明 | メーカ |
IS61DDPB24M18 | DDR-IIP (Burst of 2) CIO Synchronous SRAMs | Integrated Silicon Solution |
IS61DDPB24M18A | 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM | Integrated Silicon Solution |
IS61DDPB24M18A1 | 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM | Integrated Silicon Solution |
IS61DDPB24M18A2 | 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM | Integrated Silicon Solution |