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IS61DDP2B42M36A1 の電気的特性と機能

IS61DDP2B42M36A1のメーカーはIntegrated Silicon Solutionです、この部品の機能は「72Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS61DDP2B42M36A1
部品説明 72Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS61DDP2B42M36A1 Datasheet, IS61DDP2B42M36A1 PDF,ピン配置, 機能
IS61DDP2B44M18A/A1/A2
IS61DDP2B42M36A/A1/A2
4Mx18, 2Mx36
72Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM
(2.0 Cycle Read Latency)
ADVANCED INFORMATION
JULY 2012
FEATURES
DESCRIPTION
2Mx36 and 4Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data
valid window.
Common I/O read and write ports.
Synchronous pipeline read with self-timed late write
operation.
Double Data Rate (DDR) interface for read and
write input ports.
2.0 cycle read latency.
Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control
registering at rising edges only.
Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data.
+1.8V core power supply and 1.5V to 1.8V VDDQ,
used with 0.75 to 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte
writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1
functions.
Byte write capability.
Fine ball grid array (FBGA) package:
13mm x 15mm & 15mm x 17mm body size
165-ball (11 x 15) array
Programmable impedance output drivers via 5x
user-supplied precision resistor.
Data Valid Pin (QVLD).
ODT (On Die Termination) feature is supported
optionally on data inputs, K/K#, and BWx#.
The end of top mark (A/A1/A2) is to define options.
IS61DDP2B42M36A : Don’t care ODT function
and pin connection
IS61DDP2B42M36A1 : Option1
IS61DDP2B42M36A2 : Option2
Refer to more detail description at page 6 for each
ODT option.
The 72Mb IS61DDP2B42M36A/A1/A2 and
IS61DDP2B44M18A/A1/A2 are synchronous, high-
performance CMOS static random access memory (SRAM)
devices. These SRAMs have a common I/O bus. The rising
edge of K clock initiates the read/write operation, and all
internal operations are self-timed. Refer to the Timing
Reference Diagram for Truth Table for a description of the
basic operations of these DDR-IIP (Burst of 4) CIO SRAMs.
Read and write addresses are registered on alternating rising
edges of the K clock. Reads and writes are performed in
double data rate.
The following are registered internally on the rising edge of
the K clock:
Read/write address
Read enable
Write enable
Byte writes
Data-in for first and third burst addresses
Data-out for first and third burst addresses
The following are registered on the rising edge of the K#
clock:
Byte writes
Data-in for second and fourth burst addresses
Data-out for second and fourth burst addresses
Byte writes can change with the corresponding data-in to
enable or disable writes on a per-byte basis. An internal write
buffer enables the data-ins to be registered one cycle after
the write address. The first data-in burst is clocked one cycle
later than the write command signal, and the second burst is
timed to the following rising edge of the K# clock. Two full
clock cycles are required to complete a write operation.
During the burst read operation, the data-outs from the first
bursts are updated from output registers of the second rising
edge of the K clock (starting two cycles later after read
command). The data-outs from the second burst are updated
with the third rising edge of the K# clock where read
command receives at the first rising edge of K.
The device is operated with a single +1.8V power supply and
is compatible with HSTL I/O interfaces.
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
7/05/2012
1

1 Page





IS61DDP2B42M36A1 pdf, ピン配列
IS61DDP2B44M18A/A1/A2
IS61DDP2B42M36A/A1/A2
Ball Descriptions
Symbol
K, K#
CQ, CQ#
Doff#
QVLD
SA
DQ0 - DQn
R/W#
LD#
BWx#
VREF
VDD
VDDQ
VSS
ZQ
TMS, TDI, TCK
Type
Input
Output
Input
Output
Input
Bidir
Input
Input
Input
Input
reference
Power
Power
Ground
Input
Input
Description
Input clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.
These balls cannot remain VREF level.
Synchronous echo clock outputs: The edges of these outputs are tightly matched to the synchronous
data outputs and can be used as a data valid indication. These signals are free running clocks and
do not stop when Q tri-states.
DLL disable and reset input : When low, this input causes the DLL to be bypassed and reset the
previous DLL information. When high, DLL will start operating and lock the frequency after tCK lock
time. The device behaves in one read latency mode when the DLL is turned off. In this mode, the
device can be operated at a frequency of up to 167 MHz.
Valid output indicator: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and
CQ#.
Synchronous address inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. These inputs are ignored when device is deselected.
Data input and output signals. Input data must meet setup and hold times around the rising edges of
K and K# during WRITE operations. These pins drive out the requested data when the read
operation is active. Valid output data is synchronized to the respective CQ and CQ#.
See BALL CONFIGURATION figures for ball site location of individual signals.
The x18 device uses DQ0~DQ17. DQ18~DQ35 should be treated as NC pin.
The x36 device uses DQ0~DQ35.
Synchronous Read or Write input. When LD# is low, this input designates the access type (read
when it is High, write when it is Low) for loaded address. R/W# must meet the setup and hold times
around edge of K.
Synchronous load. This input is brought Low when a bus cycle sequence is defined. This definition
includes address and read/write direction.
Synchronous byte writes: When low, these inputs cause their respective byte to be registered and
written during WRITE cycles. These signals are sampled on the same edge as the corresponding
data and must meet setup and hold times around the rising edges of K and K# for each of the two
rising edges comprising the WRITE cycle. See Write Truth Table for signal to data relationship.
HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise
margin. Provides a reference voltage for the HSTL input buffers.
Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.
Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating
Conditions for range.
Ground of the device
Output impedance matching input: This input is used to tune the device outputs to the system data
bus impedance. Q and CQ output impedance are set to 0.2xRQ, where RQ is a resistor from this ball
to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance
mode. This ball cannot be connected directly to VSS or left unconnected.
In ODT (On Die Termination) enable devices, the ODT termination values tracks the value of RQ.
The ODT range is selected by ODT control input.
IEEE 1149.1 input pins for JTAG
TDO
NC
ODT
Output
N/A
Input
IEEE 1149.1 output pins for JTAG
No connect: These signals should be left floating or connected to ground to improve package heat
dissipation.
ODT control; Refer to SRAM features for the details.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
7/05/2012
3


3Pages


IS61DDP2B42M36A1 電子部品, 半導体
IS61DDP2B44M18A/A1/A2
IS61DDP2B42M36A/A1/A2
ODT (On Die Termination)
On Die Termination (ODT) is a feature that allows a SRAM to turn on/off termination resistance for ODT pins. The ODT
feature is designed to improve signal integrity of the memory channel by allowing the SRAM controller to turn on/off
termination resistance independently for any or all SRAM devices.
ODT can have three status, High, Low, and Floating. Each status can have different ODT termination values which
tracks the value of RQ (See the picture below) In DDR-IIP devices having common I/O bus, ODT is automatically
enabled at the write operation of SRAM and disabled at the read operation of SRAM.
Fig1. Functional representation of ODT
VDDQ
VDDQ VDDQ
ODT=L ODT=H ODT=Floating
R1x2
R2x2
R3x2
R1x2
R2x2
PAD
R3x2
ODT=L ODT=H ODT=Floating
VSS
VSS
VSS
R1 R2 R3
Option13
0.3x
RQ1
0.6x
RQ2
0.6x
RQ2
Option24
ODT
disable
0.6x
RQ2
ODT
disable
Notes
1. Allowable range of RQ to guarantee impedance matching a tolerance of ±20% is 175<RQ<350.
2. Allowable range of RQ to guarantee impedance matching a tolerance of ±20% is 175<RQ<250.
3. ODT control pin is connected to VDDQ through 3.5k. Therefore it is recommended to connect it to VSS
through less than 100to make it low.
4. ODT control pin is connected to VSS through 3.5k. Therefore it is recommended to connect it to VDDQ
through less than 100to make it high.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
7/05/2012
6

6 Page



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部品番号部品説明メーカ
IS61DDP2B42M36A

72Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM

Integrated Silicon Solution
Integrated Silicon Solution
IS61DDP2B42M36A1

72Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM

Integrated Silicon Solution
Integrated Silicon Solution
IS61DDP2B42M36A2

72Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM

Integrated Silicon Solution
Integrated Silicon Solution


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