IS61DDB42M18 Datasheet PDF - Integrated Silicon Solution
| Part Number | IS61DDB42M18 | |
| Description | DDR-II (Burst of 4) CIO Synchronous SRAMs | |
| Manufacturers | Integrated Silicon Solution | |
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36 Mb (1M x 36. & 2M x 18)
ISSIDDR-II (Burst of 4) CIO Synchronous SRAMs
®
Features
• 1M x 36 or 2M x 18.
• On-chip delay-locked loop (DLL) for wide data
valid window.
• Common I/O read and write ports.
• Synchronous pipeline read with late write opera-
tion.
• Double data rate (DDR-II) interface for read and
write input ports.
• Fixed 4-bit burst for read and write operations.
• Clock stop support.
• Two input clocks (K and K) for address and con-
trol registering at rising edges only.
• Two input clocks (C and C) for data output con-
trol.
May 2005
• Two echo clocks (CQ and CQ) that are delivered
simultaneously with data.
• +1.8V core power supply and 1.5, 1.8V VDDQ,
used with 0.75, 0.9V VREF.
• HSTL input and output levels.
• Registered addresses, write and read controls,
byte writes, and data outputs.
• Full data coherency.
• Boundary scan using limited set of JTAG 1149.1
functions.
• Byte write capability.
• Fine ball grid array (FBGA) package
- 15mm x 17mm body size
- 1mm pitch
- 165-ball (11 x 15) array
• Programmable impedance output drivers via 5x
user-supplied precision resistor.
Description
The 36Mb IS61DDB41M36 and IS61DDB42M18
are synchronous, high-performance CMOS static
random access memory (SRAM) devices. These
SRAMs have a common I/O bus. The rising edge of
K clock initiates the read/write operation, and all
internal operations are self-timed. Refer to the
Timing Reference Diagram for Truth Table on p.8
for a description of the basic operations of these
DDR-II (Burst of 4) CIO SRAMs.
Read and write addresses are registered on alter-
nating rising edges of the K clock. Reads and writes
are performed in double data rate. The following are
registered internally on the rising edge of the K
clock:
• Read and write addresses
• Address load
• Read/write enable
• Byte writes for burst addresses 1 and 3
• Data-in for burst addresses 1 and 3
The following are registered on the rising edge of
the K clock:
• Byte writes for burst addresses 2 and 4
• Data-in for burst addresses 2 and 4
Byte writes can change with the corresponding data-
in to enable or disable writes on a per-byte basis. An
internal write buffer enables the data-ins to be regis-
tered one cycle later than the write address. The first
data-in burst is clocked one cycle later than the write
command signal, and the second burst is timed to
the following rising edge of the K clock. Two full
clock cycles are required to complete a write opera-
tion.
During the burst read operation, at the first and third
bursts the data-outs are updated from output regis-
ters off the second and fourth rising edges of the C
clock (starting 1.5 cycles later). At the second and
fourth bursts, the data-outs are updated with the
third and fifth rising edges of the corresponding C
clock (see page 9). The K and K clocks are used to
time the data-outs whenever the C and C clocks are
tied high. Two full clock cycles are required to
complete a read operation
The device is operated with a single +1.8V power
supply and is compatible with HSTL I/O interfaces.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/09/04
1
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36 Mb (1M x 36 & 2M x 18)
DDR-II (Burst of 4) CIO Synchronous SRAMs
ISSI®
The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the
burst, is presented 1 cycle later or at the rising edge of the following K clock. The data-in corresponding to the
second write burst address follows next, registered by the rising edge of K. The third data-out is clocked by
the subsequent rising edge of the K clock, and the fourth data-out is clocked by the subsequent rising edge of
the K clock.
The data-in provided for writing is initially kept in write buffers. The information on these buffers is written into
the array on the third write cycle. A read cycle to the last two write address produces data from the write
buffers. The SRAM maintains data coherency.
During a write, the byte writes independently control which byte of any of the four burst addresses is written
(see X18/X36 Write Truth Tables on page 9 and Timing Reference Diagram for Truth Table on page 8).
Whenever a write is disabled (R/W is high at the rising edge of K), data is not written into the memory.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM
to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance
driven by the SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range
of RQ to guarantee impedance matching is between 175Ω and 350Ω, with the tolerance described in
Programmable Impedance Output Driver DC Electrical Characteristics on page 15. The RQ resistor should
be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded
ZQ trace must be less than 3 pF.
The ZQ pin can also be directly connected to VDDQ to obtain a minimum impedance setting. ZQ must never
be connected to VSS.
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by
drifts in supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable
impedances values. The final impedance value is achieved within 1024 clock cycles.
Clock Consideration
This device uses an internal DLL for maximum output data valid window. It can be placed in a stopped-clock
mode to minimize power and requires only 1024 cycles to restart.
No clocks can be issued until VDD reaches its allowable operating range.
Single Clock Mode
This device can be also operated in single-clock mode. In this case, C and C are both connected high at
power-up and must never change. Under this condition, K and K control the output timings.
Either clock pair must have both polarities switching and must never connect to VREF, as they are not differ-
ential clocks.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/09/04
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for IS61DDB42M18 electronic component. |
| Information | Total 26 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ IS61DDB42M18.PDF Datasheet ] | |
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