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IS61DDB41M36 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 IS61DDB41M36
部品説明 DDR-II (Burst of 4) CIO Synchronous SRAMs
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 



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IS61DDB41M36 Datasheet, IS61DDB41M36 PDF,ピン配置, 機能
36 Mb (1M x 36. & 2M x 18)
ISSIDDR-II (Burst of 4) CIO Synchronous SRAMs
®
Features
• 1M x 36 or 2M x 18.
• On-chip delay-locked loop (DLL) for wide data
valid window.
• Common I/O read and write ports.
• Synchronous pipeline read with late write opera-
tion.
• Double data rate (DDR-II) interface for read and
write input ports.
• Fixed 4-bit burst for read and write operations.
• Clock stop support.
• Two input clocks (K and K) for address and con-
trol registering at rising edges only.
• Two input clocks (C and C) for data output con-
trol.
May 2005
• Two echo clocks (CQ and CQ) that are delivered
simultaneously with data.
• +1.8V core power supply and 1.5, 1.8V VDDQ,
used with 0.75, 0.9V VREF.
• HSTL input and output levels.
• Registered addresses, write and read controls,
byte writes, and data outputs.
• Full data coherency.
• Boundary scan using limited set of JTAG 1149.1
functions.
• Byte write capability.
• Fine ball grid array (FBGA) package
- 15mm x 17mm body size
- 1mm pitch
- 165-ball (11 x 15) array
• Programmable impedance output drivers via 5x
user-supplied precision resistor.
Description
The 36Mb IS61DDB41M36 and IS61DDB42M18
are synchronous, high-performance CMOS static
random access memory (SRAM) devices. These
SRAMs have a common I/O bus. The rising edge of
K clock initiates the read/write operation, and all
internal operations are self-timed. Refer to the
Timing Reference Diagram for Truth Table on p.8
for a description of the basic operations of these
DDR-II (Burst of 4) CIO SRAMs.
Read and write addresses are registered on alter-
nating rising edges of the K clock. Reads and writes
are performed in double data rate. The following are
registered internally on the rising edge of the K
clock:
• Read and write addresses
• Address load
• Read/write enable
• Byte writes for burst addresses 1 and 3
• Data-in for burst addresses 1 and 3
The following are registered on the rising edge of
the K clock:
• Byte writes for burst addresses 2 and 4
• Data-in for burst addresses 2 and 4
Byte writes can change with the corresponding data-
in to enable or disable writes on a per-byte basis. An
internal write buffer enables the data-ins to be regis-
tered one cycle later than the write address. The first
data-in burst is clocked one cycle later than the write
command signal, and the second burst is timed to
the following rising edge of the K clock. Two full
clock cycles are required to complete a write opera-
tion.
During the burst read operation, at the first and third
bursts the data-outs are updated from output regis-
ters off the second and fourth rising edges of the C
clock (starting 1.5 cycles later). At the second and
fourth bursts, the data-outs are updated with the
third and fifth rising edges of the corresponding C
clock (see page 9). The K and K clocks are used to
time the data-outs whenever the C and C clocks are
tied high. Two full clock cycles are required to
complete a read operation
The device is operated with a single +1.8V power
supply and is compatible with HSTL I/O interfaces.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/09/04
1

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