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IS61DDB42M18A の電気的特性と機能

IS61DDB42M18AのメーカーはIntegrated Silicon Solutionです、この部品の機能は「36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS61DDB42M18A
部品説明 36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS61DDB42M18A Datasheet, IS61DDB42M18A PDF,ピン配置, 機能
IS61DDB42M18A
IS61DDB41M36A
2Mx18, 1Mx36
36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM
JANUARY 2015
FEATURES
DESCRIPTION
1Mx36 and 2Mx18 configuration available.
On-chip delay-locked loop (DLL) for wide data valid
window.
Common I/O read and write ports.
Synchronous pipeline read with late write operation.
Double Data Rate (DDR) interface for read and
write input ports.
Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control
registering at rising edges only.
Two input clocks (C and C#) for data output control.
Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data.
+1.8V core power supply and 1.5V to1.8V VDDQ,
used with 0.75V to 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte
writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1
functions.
Byte write capability.
Fine ball grid array (FBGA) package:
13mmx15mm and 15mmx17mm body size
165-ball (11 x 15) array
Programmable impedance output drivers via 5x
user-supplied precision resistor.
The 36Mb IS61DDB41M36A and IS61DDB42M18A are
synchronous, high-performance CMOS static random access
memory (SRAM) devices. These SRAMs have a common I/O
bus. The rising edge of K clock initiates the read/write
operation, and all internal operations are self-timed. Refer to
the Timing Reference Diagram for Truth Table for a
description of the basic operations of these DDR-II (Burst of
4) CIO SRAMs.
Read and write addresses are registered on alternating rising
edges of the K clock. Reads and writes are performed in
double data rate.
The following are registered internally on the rising edge of
the K clock:
Read/write address
Read enable
Write enable
Byte writes for burst addresses first and third
Data-in for burst addresses first and third
The following are registered on the rising edge of the K#
clock:
Byte writes for burst addresses second and fourth
Data-in for burst addresses second and fourth
Byte writes can change with the corresponding data-in to
enable or disable writes on a per-byte basis. An internal write
buffer enables the data-ins to be registered one cycle after
the write address. The first data-in burst is clocked one cycle
later than the write command signal, and the second burst is
timed to the following rising edge of the K# clock. Two full
clock cycles are required to complete a write operation.
During the burst read operation, the data-outs from the first
and third bursts are updated from output registers of the
second and third rising edges of the C# clock (starting on and
half cycles later after read command). The data-outs from the
second and fourth bursts are updated with the third and
fourth rising edges of the C clock. The K and K# clocks are
used to time the data-outs whenever the C and C# clocks are
tied high. Two full clock cycles are required to complete a
read operation.
The device is operated with a single +1.8V power supply and
is compatible with HSTL I/O interfaces.
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
10/02/2014
1

1 Page





IS61DDB42M18A pdf, ピン配列
IS61DDB42M18A
IS61DDB41M36A
Ball Description
Symbol
K, K#
C, C#
CQ, CQ#
Doff#
SA
DQ0 - DQn
R/W#
LD#
BWx#
VREF
VDD
VDDQ
VSS
ZQ
TMS, TDI,
TCK
TDO
NC
Type
Input
Input
Output
Input
Input
Bidir
Input
Input
Input
Input
reference
Power
Power
Description
Input clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.
These balls cannot remain VREF level.
Input clock for output data. C and C# are used to clock out the READ data. They can be used
together to deskew the flight times of various devices on the board back to the controller. See
application example for further details.
Synchronous echo clock outputs: The edges of these outputs are tightly matched to the
synchronous data outputs and can be used as a data valid indication. These signals are free running
clocks and do not stop when Q tri-states.
DLL disable and reset input : when low, this input causes the DLL to be bypassed and reset the
previous DLL information. When high, DLL will start operating and lock the frequency after tCK lock
time. The device behaves in one read latency mode when the DLL is turned off. In this mode, the
device can be operated at a frequency of up to 167 MHz.
Synchronous address inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. These inputs are ignored when device is deselected.
Data input and output signals. Input data must meet setup and hold times around the rising edges of
K and K# during WRITE operations. These pins drive out the requested data when the read
operation is active. Valid output data is synchronized to the respective C and C#, or to the
respective K and K# if C and /C are tied to high. When read access is deselected, DQ0 - DQn are
automatically tri-stated.
See BALL CONFIGURATION figures for ball site location of individual signals.
The x18 device uses DQ0~DQ17. DQ18~DQ35 should be treated as NC pin.
The x36 device uses DQ0~DQ35.
Synchronous Read or Write input. When LD# is low, this input designates the access type (read
when it is High, write when it is Low) for loaded address. R/W# must meet the setup and hold times
around edge of K.
Synchronous load. This input is brought Low when a bus cycle sequence is defined. This definition
includes address and read/write direction.
Synchronous byte writes: When low, these inputs cause their respective byte to be registered and
written during WRITE cycles. These signals are sampled on the same edge as the corresponding
data and must meet setup and hold times around the rising edges of K and #K for each of the two
rising edges comprising the WRITE cycle. See Write Truth Table for signal to data relationship.
HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise
margin. Provides a reference voltage for the HSTL input buffers.
Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.
Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating
Conditions for range.
Ground Ground of the device
Input
Output impedance matching input: This input is used to tune the device outputs to the system data
bus impedance. DQ and CQ output impedance are set to 0.2xRQ, where RQ is a resistor from this
ball to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance
mode. This ball cannot be connected directly to VSS or left unconnected.
Input
IEEE1149.1 input pins for JTAG.
Output
N/A
IEEE1149.1 output pins for JTAG.
No connect: These signals should be left floating or connected to ground to improve package heat
dissipation.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
10/02/2014
3


3Pages


IS61DDB42M18A 電子部品, 半導体
IS61DDB42M18A
IS61DDB41M36A
The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K#
for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is
not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being
reset, it gets locked after 2048 cycles of stable clock.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
10/02/2014
6

6 Page



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部品番号部品説明メーカ
IS61DDB42M18

DDR-II (Burst of 4) CIO Synchronous SRAMs

Integrated Silicon Solution
Integrated Silicon Solution
IS61DDB42M18A

36Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM

Integrated Silicon Solution
Integrated Silicon Solution


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