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IS61DDB21M36 の電気的特性と機能

IS61DDB21M36のメーカーはIntegrated Silicon Solutionです、この部品の機能は「DDR-II (Burst of 2) CIO Synchronous SRAMs」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS61DDB21M36
部品説明 DDR-II (Burst of 2) CIO Synchronous SRAMs
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS61DDB21M36 Datasheet, IS61DDB21M36 PDF,ピン配置, 機能
36 Mb (1M x 36. & 2M x 18)
ISSIDDR-II (Burst of 2) CIO Synchronous SRAMs
®
Features
• 1M x 36 or 2M x 18.
• On-chip delay-locked loop (DLL) for wide data
valid window.
• Common data input/output bus.
• Synchronous pipeline read with self-timed late
write operation.
• Double data rate (DDR-II) interface for read and
write input ports.
• Fixed 2-bit burst for read and write operations.
• Clock stop support.
• Two input clocks (K and K) for address and con-
trol registering at rising edges only.
• Two input clocks (C and C) for data output con-
trol.
May 2005
• Two echo clocks (CQ and CQ) that are delivered
simultaneously with data.
• +1.8V core power supply and 1.5, 1.8V VDDQ,
used with 0.75, 0.9V VREF.
• HSTL input and output levels.
• Registered addresses, write and read controls,
byte writes, data in, and data outputs.
• Full data coherency.
• Boundary scan using limited set of JTAG 1149.1
functions.
• Byte write capability.
• Fine ball grid array (FBGA) package
- 15mm x 17mm body size
- 1mm pitch
- 165-ball (11 x 15) array
• Programmable impedance output drivers via 5x
user-supplied precision resistor.
Description
The 36Mb IS61DDB21M36 and
IS61DDB22M18 are synchronous, high-perfor-
mance CMOS static random access memory
(SRAM) devices. These SRAMs have a common I/O
bus. The rising edge of K clock initiates the
read/write operation, and all internal operations are
self-timed.
Refer to the Timing Reference Diagram for Truth
Table on page 8 for a description of the basic opera-
tions of these DDR-II (Burst of 2) CIO SRAMs.
The input addresses are registered on all rising
edges of the K clock. The DQ bus operates at
double data rate for reads and writes. The following
are registered internally on the rising edge of the K
clock:
• Read and write addresses
• Address load
• Read/write enable
• Byte writes
• Data-in
The following are registered on the rising edge of
the K clock:
• Byte writes
• Data-in for second burst addresses
Byte writes can change with the corresponding data-
in to enable or disable writes on a per-byte basis. An
internal write buffer enables the data-ins to be regis-
tered one cycle later than the write address. The first
data-in burst is clocked with the rising edge of the
next K clock, and the second burst is timed to the
following rising edge of the K clock.
During the burst read operation, at the first burst the
data-outs are updated from output registers off the
second rising edge of the C clock (1.5 cycles later).
At the second burst, the data-outs are updated with
the third rising edge of the corresponding C clock
(see page 9). The K and K clocks are used to time
the data-outs whenever the C and C clocks are tied
high.
The device is operated with a single +1.8V power
supply and is compatible with HSTL I/O interfaces.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
2/22/05
1

1 Page





IS61DDB21M36 pdf, ピン配列
36 Mb (1M x 36 & 2M x 18)
DDR-II (Burst of 2) CIO Synchronous SRAMs
ISSI®
Pin Description
Symbol
Pin Number
Description
K, K 6B, 6A
Input clock.
C, C
6P, 6R
Input clock for output data control.
CQ, CQ
11A, 1A
Output echo clock.
Doff 1H
DLL disable when low.
SA0 6C
Burst count address input.
SA
9A, 4B, 8B, 5C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R, 5R, 7R,
8R, 9R
1M x 36 address inputs.
SA
3A, 9A, 4B, 8B, 5C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R, 4R, 5R,
7R, 8R, 9R
2M x 18 address inputs.
DQ0–DQ8
DQ9–DQ17
DQ18–DQ26
DQ27–DQ35
11P, 11M, 11L, 11K, 11J, 11F, 11E, 11C, 11B
10P, 11N, 10M, 10K, 10J, 11G, 10E, 11D, 10C
3B, 3D, 3E, 3F, 3G, 3K, 3L, 3N, 3P
2B, 3C, 2D, 2F, 2G, 3J, 2L, 3M, 2N
1M x 36 DQ pins
DQ0–DQ8
DQ9–DQ17
11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B
2B, 3D, 3E, 2F, 3G, 3K, 2L, 3N, 3P
2M x 18 DQ pins
R/W 4A
Read/write control. Read when active high.
LD 8A
Synchronizes load. Loads new address
when low.
BW0, BW1, BW2, BW3 7B, 7A, 5A,5B
1M x 36 byte write control, active low.
BW0, BW1
7B, 5A
2M x 18 byte write control, active low.
VREF
2H, 10H
Input reference level.
VDD 5F, 7F, 5G, 7G, 5H, 7H, 5J, 7J, 5K, 7K
Power supply.
VDDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output power supply.
VSS
2A, 10A, 4C, 8C, 4D, 5D, 6D, 7D, 8D, 5E, 6E, 7E, 6F, 6G, 6H, 6J,
6K, 5L, 6L, 7L, 4M, 8M, 4N, 8N
Power supply.
ZQ 11H
Output driver impedance control.
TMS, TDI, TCK
10R, 11R, 2R
IEEE 1149.1 test inputs (1.8V LVTTL lev-
els).
TDO
1R
IEEE 1149.1 test output (1.8V LVTTL level).
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
2/22/05
3


3Pages


IS61DDB21M36 電子部品, 半導体
36 Mb (1M x 36 & 2M x 18)
DDR-II (Burst of 2) CIO Synchronous SRAMs
ISSI®
Depth Expansion
The following figure depicts an implementation of four 2M x 18 DDR-II SRAMs with common I/Os. In this appli-
cation example, the second pair of C and C clocks is delayed such that the return data meets the data setup
and hold times at the bus master.
Application Example
2M x 18
Vt
R
Data-In/Data-Out
0–71
Address 0–65
SRAM #1
ZQ R=250
DQ0–17
SA LD R/W BW0 BW1 C C K K
LD
R/W
BW0–7
Memory
Controller
Return CLK
Source CLK
Return CLK
Source CLK
Vt
Vt
R=50Vt=VREF
SRAM #4
ZQ R=250
DQ0–17
SA LD R/W BW0 BW1 C C K K
Vt
R
Power-Up and Power-Down Sequences
The power supplies must be powered up in the following order:
1. VDD
2. VDDQ
3. VREF
4. Inputs
The power-down sequence must be the reverse. VDDQ can be allowed to exceed VDD by no more than 0.6V.
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
2/22/05

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
IS61DDB21M36

DDR-II (Burst of 2) CIO Synchronous SRAMs

Integrated Silicon Solution
Integrated Silicon Solution
IS61DDB21M36A

36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM

Integrated Silicon Solution
Integrated Silicon Solution


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