PDF IS61NVVP409618B Data sheet ( Hoja de datos )

Número de pieza	IS61NVVP409618B
Descripción	PIPELINE (NO WAIT) STATE BUS SRAM
Fabricantes	Integrated Silicon Solution
Logotipo
Hay una vista previa y un enlace de descarga de IS61NVVP409618B (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! IS61NLP204836B/IS61NVP/NVVP204836B IS61NLP409618B/IS61NVP/NVVP409618B 2M x 36 and 4M x 18 AUGUST 2014 72Mb, PIPELINE 'NO WAIT' STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control us- ing MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 165-ball PBGA and 119- ball PBGA packages • Power supply: NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NVVP: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%) • JTAG Boundary Scan for PBGA packages • Industrial temperature available • Lead-free available FAST ACCESS TIME Symbol tkq tkc Parameter Clock Access Time Cycle Time Frequency 250 200 2.8 3.1 45 250 200 DESCRIPTION The 72 Meg product family features high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 2,096,952 words by 36 bits and 4,193,904 words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by theADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. 166 Units 3.8 ns 6 ns 166 MHz Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1 Rev. A 8/4/2014 1 page IS61NLP204836B/IS61NVP/NVVP204836B IS61NLP409618B/IS61NVP/NVVP409618B 119-PIN PBGA PACKAGE CONFIGURATION 1234 A VDDQ A A A B NC CE2 A ADV C NC A A VDD D DQc DQPc VSS NC E DQc DQc VSS CE F VDDQ DQc VSS OE G DQc DQc BWc A H DQc DQc VSS WE J VDDQ VDD NC VDD K DQd DQd VSS CLK L DQd DQd BWd NC M VDDQ DQd VSS CKE N DQd DQd VSS A1* P DQd DQPd VSS A0* R NC A MODE VDD T NC A A A U VDDQ TMS TDI TCK 2M x 36 (TOP VIEW) 56 AA A CE2 AA VSS DQPb VSS DQb VSS DQb BWb DQb VSS DQb NC VDD VSS DQa BWa DQa VSS DQa VSS DQa VSS DQPa NC A AA TDO NC 7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol Pin Name A Synchronous Address Inputs A0, A1 Synchronous Burst Address Inputs ADV Synchronous Burst Address Advance/ Load WE Synchronous Read/Write Control Input CLK Synchronous Clock CKE Synchronous Clock Enable CE Synchronous Chip Select CE2 Synchronous Chip Select CE2 Synchronous Chip Select BWa-BWd Synchronous Byte Write Inputs OE Asynchronous Output Enable ZZ Asynchronous Power Sleep Mode MODE Burst Sequence Selection TCK, TDO JTAG Pins TMS, TDI Vdd Power Supply Vss Ground NC DQa-DQd No Connect Synchronous Data Inputs/Outputs DQPa-DQPd Synchronous Parity Data Inputs/Outputs Vddq I/O Power Supply Integrated Silicon Solution, Inc. — www.issi.com Rev. A 8/4/2014 5 5 Page IS61NLP204836B/IS61NVP/NVVP204836B IS61NLP409618B/IS61NVP/NVVP409618B ASYNCHRONOUS TRUTH TABLE(1) Operation ZZ OE I/O STATUS Sleep Mode H X High-Z Read L L L H DQ High-Z Write L X Din, High-Z Deselected L X High-Z Notes: 1. X means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. 4. Deselected means power Sleep Mode where stand-by current depends on cycle time. WRITE TRUTH TABLE (x18) Operation WE BWa BWb READ H X X WRITE BYTE a L L H WRITE BYTE b L H L WRITE ALL BYTEs L L L WRITE ABORT/NOP L H H Notes: 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. Integrated Silicon Solution, Inc. — www.issi.com 11 Rev. A 8/4/2014 11 Page

Páginas	Total 30 Páginas
PDF Descargar	[ Datasheet IS61NVVP409618B.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
IS61NVVP409618B	PIPELINE (NO WAIT) STATE BUS SRAM	Integrated Silicon Solution

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar