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IS61NVVF204836B の電気的特性と機能

IS61NVVF204836BのメーカーはIntegrated Silicon Solutionです、この部品の機能は「FLOW THROUGH (NO WAIT) STATE BUS SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS61NVVF204836B
部品説明 FLOW THROUGH (NO WAIT) STATE BUS SRAM
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS61NVVF204836B Datasheet, IS61NVVF204836B PDF,ピン配置, 機能
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B 
2M x 36 and 4M x 18
72Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM
ADVANCED INFORMATION
FEBRUARY 2013
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single Read/Write control pin
• Clock controlled, registered address,
data and control
• Interleaved or linear burst sequence control us-
ing MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 119-ball PBGA, and 165-
ball PBGA packages
• Power supply:
NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%)
NVVF: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
• Lead-free available
DESCRIPTION
The 72 Meg product family features high-speed, low-power
synchronous static RAMs designed to provide a burstable,
high-performance, 'no wait' state, device for networking
and communications applications. They are organized as
2,096,952 words by 36 bits and 4,193,904 words by 18
bits, fabricated with ISSI's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by theADV
input. When the ADV is HIGH the internal burst counter
is incremented. New external addresses can be loaded
when ADV is LOW.
Write cycles are internally self-timed and are initiated
by the rising edge of the clock inputs and when WE is
LOW. Separate byte enables allow individual bytes to be
written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
FAST ACCESS TIME
Symbol Parameter
tkq
Clock Access Time
tkc
Cycle Time
Frequency
6.5
6.5
7.5
133
7.5
7.5
8.5
117
Units
ns
ns
MHz
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. 00C
02/20/2013

1 Page





IS61NVVF204836B pdf, ピン配列
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B 
165-PIN BGA
165-Ball, 13x15 mm BGA
165-Ball, 15x17 mm BGA
1mm Ball Pitch, 11x15 Ball Array
119-PIN BGA
119-Ball, 14x22 mm BGA
1.27mm Ball Pitch, 7x17 Ball Array
BOTTOM VIEW
BOTTOM VIEW
Integrated Silicon Solution, Inc. — www.issi.com 3
Rev. 00C
02/20/2013


3Pages


IS61NVVF204836B 電子部品, 半導体
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B 
165-PIN PBGA PACKAGE CONFIGURATION
12345
A NC A CE BWb NC
B NC A CE2 NC BWa
C NC NC VDDQ VSS VSS
D NC DQb VDDQ VDD VSS
E NC DQb VDDQ VDD VSS
F NC DQb VDDQ VDD VSS
G NC DQb VDDQ VDD VSS
H NC NC NC VDD VSS
J
DQb
NC VDDQ VDD VSS
K
DQb
NC VDDQ VDD VSS
L
DQb
NC VDDQ VDD VSS
M
DQb
NC VDDQ VDD VSS
N DQPb NC VDDQ VSS NC
P NC A A A TDI
R MODE A A A TMS
4M x 18 (TOP VIEW)
678
CE2 CKE ADV
CLK WE
OE
VSS VSS VSS
VSS VSS VDD
VSS VSS VDD
VSS VSS VDD
VSS VSS VDD
VSS VSS VDD
VSS VSS VDD
VSS VSS VDD
VSS VSS VDD
VSS VSS VDD
NC NC VSS
A1* TDO
A
A0* TCK
A
9
A
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
11
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
NC
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
A Synchronous Address Inputs
A0, A1
Synchronous Burst Address Inputs
ADV
Synchronous Burst Address Advance/
Load
WE Synchronous Read/Write Control Input
CLK
Synchronous Clock
CKE
Synchronous Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWa-BWb Synchronous Byte Write Inputs
OE
Asynchronous Output Enable
ZZ
Asynchronous Power Sleep
Mode
MODE
Burst Sequence Selection
TCK, TDI
TDO, TMS
JTAG Pins
VDD
Power Supply
NC No Connect
DQa-DQb Synchronous Data Inputs/Outputs
DQPa-DQPb Synchronous Parity Data
Inputs/Outputs
VDDQ
I/O Power Supply
Vss
Ground
6 Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013

6 Page



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部品番号部品説明メーカ
IS61NVVF204836B

FLOW THROUGH (NO WAIT) STATE BUS SRAM

Integrated Silicon Solution
Integrated Silicon Solution


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