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PDF IS61VPS51236B Data sheet ( Hoja de datos )
| Número de pieza | IS61VPS51236B | |
| Descripción | SINGLE CYCLE DESELECT STATIC RAM | |
| Fabricantes | Integrated Silicon Solution | |
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IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED
SINGLE CYCLE DESELECT STATIC RAM
NOVEMBER 2014
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
• control
• Burst sequence control using MODE input
• Three chip enable option for simple depth
expansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JEDEC 100-pin QFP, 165-ball BGA and 119-ball
BGA packages
• Power supply:
LPS: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)
VPS: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)
VVPS: VDD 1.8V (± 5%), VDDQ 1.8V (± 5%)
• JTAG Boundary Scan for BGA packages
• Commercial, Industrial and Automotive
temperature support
• Lead-free available
• For leaded options, please contact ISSI
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access
Time
Cycle time
Frequency
-250
2.6
4
250
-200
3.0
5
200
Units
ns
ns
MHz
DESCRIPTION
The 18Mb product family features high-speed, low-
power synchronous static RAMs designed to provide
burstable, high-performance memory for
communication and networking applications. The
IS61LPS/VPS/VVPS51236B are organized as 524,288
words by 36bits. The IS61LPS/VPS/VVPS102418B are
organized as 1,048,576 words by 18bits. Fabricated
with ISSI's advanced CMOS technology, the device
integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single
monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single
clock input.
Write cycles are internally self-timed and are initiated
by the rising edge of the clock input. Write cycles can
be one to four bytes wide as controlled by the write
control inputs.
Separate byte enables allow individual bytes to be
written. The byte write operation is performed by using
the byte write enable (/BWE) input combined with one
or more individual byte write signals (/BWx). In
addition, Global Write (/GW) is available for writing all
bytes at one time, regardless of the byte write controls.
Bursts can be initiated with either /ADSP (Address
Status Processor) or /ADSC (Address Status Cache
Controller) input pins. Subsequent burst addresses can
be generated internally and controlled by the /ADV
(burst address advance) input pin.
The mode pin is used to select the burst sequence
order. Linear burst is achieved when this pin is tied
LOW. Interleave burst is achieved when this pin is tied
HIGH or left floating.
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/16/2014
1
1 page  
IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
512K x 36, 119-Ball BGA (Top View)
12
A VDDQ A
B NC A
C NC A
D DQc DQPc
E
DQc
DQc
F
VDDQ
DQc
G
DQc
DQc
H
DQc
DQc
J
VDDQ
VDD
K
DQd
DQd
L
DQd
DQd
M
VDDQ
DQd
N
DQd
DQd
P DQd DQPd
R NC A
T NC NC
U
VDDQ
TMS
3
A
A
A
VSS
VSS
VSS
/BWc
VSS
NC
VSS
/BWd
VSS
VSS
VSS
MODE
A
TDI
4
/ADSP
/ADSC
VDD
NC
/CE
/OE
/ADV
/GW
VDD
CLK
NC
/BWE
A1*
A0*
VDD
A
TCK
5
A
A
A
VSS
VSS
VSS
/BWb
VSS
NC
VSS
/BWa
VSS
VSS
VSS
NC
A
TDO
6
A
A
A
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
NC
NC
7
VDDQ
NC
NC
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
ZZ
VDDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
Bottom View
119-Ball, 14 mm x 22 mm BGA
PIN DESCRIPTIONS
Symbol
Pin Name
CLK Synchronous Clock
A0,A1
Synchronous Burst Address Inputs
A Address Inputs
/ADV
Synchronous Burst Address Advance
/ADSP
Address Status Processor
/ADSC
Address Status Controller
MODE
Burst Sequence Selection
/CE Synchronous Chip Enable
/BWE
Byte Write Enable
/BWx (x=a-d)
Synchronous Byte Write Inputs
/GW
Global Write Enable
/OE Output Enable
DQx
TCK,TDI,
TDO,TMS
ZZ
Data Inputs/Outputs
JTAG Pins
Power Sleep Mode
NC No Connect
VDD
VDDQ
VSS
Power Supply
I/O Power Supply
Ground
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/16/2014
5
5 Page 
IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
Tstg
Storage Temperature
LPS Value
–65 to +150
VPS/VVPS Value Unit
–65 to +150
°C
Pd Power Dissipation
1.6 1.6
W
Iout Output Current (per I/O)
20
Vin, Vout Voltage Relative to Vss for I/O Pins
–0.5 to VDDQ +0.3
Vin Voltage Relative to Vss for Address and –0.3 to VDD +0.5
20
–0.5 to VDDQ + 0.3
–0.3 to VDD + 0.3
mA
V
V
Control Inputs
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to
avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE (IS61LPSx)
Range
Commercial
Industrial
Automotive
Ambient Temperature
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
VDD
3.3V ± 5%
3.3V ± 5%
3.3V ± 5%
VDDQ
3.3V / 2.5V ± 5%
3.3V / 2.5V ± 5%
3.3V / 2.5V ± 5%
OPERATING RANGE (IS61VPSx)
Range
Commercial
Industrial
Automotive
Ambient Temperature
0°C to +70°C
-40°C to +85°C
VDD
VDDQ
2.5V ± 5%
2.5V ± 5%
2.5V ± 5%
2.5V ± 5%
*Please contact ISSI
OPERATING RANGE (IS61VVPSx)
Range
Commercial
Ambient Temperature
0°C to +70°C
Industrial
Automotive
-40°C to +85°C
VDD
VDDQ
1.8V ± 5%
1.8V ± 5%
1.8V ± 5%
1.8V ± 5%
*Please contact ISSI
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/16/2014
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IS61VPS51236B.PDF ] | |
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