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IS61LPS51236B の電気的特性と機能

IS61LPS51236BのメーカーはIntegrated Silicon Solutionです、この部品の機能は「SINGLE CYCLE DESELECT STATIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS61LPS51236B
部品説明 SINGLE CYCLE DESELECT STATIC RAM
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS61LPS51236B Datasheet, IS61LPS51236B PDF,ピン配置, 機能
IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
512K x36 and 1024K x18 18Mb SYNCHRONOUS PIPELINED
SINGLE CYCLE DESELECT STATIC RAM
NOVEMBER 2014
FEATURES
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Burst sequence control using MODE input
Three chip enable option for simple depth
expansion and address pipelining
Common data inputs and data outputs
Auto Power-down during deselect
Single cycle deselect
Snooze MODE for reduced-power standby
JEDEC 100-pin QFP, 165-ball BGA and 119-ball
BGA packages
Power supply:
LPS: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)
VPS: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)
VVPS: VDD 1.8V (± 5%), VDDQ 1.8V (± 5%)
JTAG Boundary Scan for BGA packages
Commercial, Industrial and Automotive
temperature support
Lead-free available
For leaded options, please contact ISSI
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access
Time
Cycle time
Frequency
-250
2.6
4
250
-200
3.0
5
200
Units
ns
ns
MHz
DESCRIPTION
The 18Mb product family features high-speed, low-
power synchronous static RAMs designed to provide
burstable, high-performance memory for
communication and networking applications. The
IS61LPS/VPS/VVPS51236B are organized as 524,288
words by 36bits. The IS61LPS/VPS/VVPS102418B are
organized as 1,048,576 words by 18bits. Fabricated
with ISSI's advanced CMOS technology, the device
integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single
monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single
clock input.
Write cycles are internally self-timed and are initiated
by the rising edge of the clock input. Write cycles can
be one to four bytes wide as controlled by the write
control inputs.
Separate byte enables allow individual bytes to be
written. The byte write operation is performed by using
the byte write enable (/BWE) input combined with one
or more individual byte write signals (/BWx). In
addition, Global Write (/GW) is available for writing all
bytes at one time, regardless of the byte write controls.
Bursts can be initiated with either /ADSP (Address
Status Processor) or /ADSC (Address Status Cache
Controller) input pins. Subsequent burst addresses can
be generated internally and controlled by the /ADV
(burst address advance) input pin.
The mode pin is used to select the burst sequence
order. Linear burst is achieved when this pin is tied
LOW. Interleave burst is achieved when this pin is tied
HIGH or left floating.
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/16/2014
1

1 Page





IS61LPS51236B pdf, ピン配列
IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
PIN CONFIGURATION
512K x 36, 165-Ball BGA (Top View)
1 23 4
A NC
A
B NC
A
C DQPc NC
D DQc DQc
E DQc DQc
F DQc DQc
G DQc DQc
H NC
VSS
J DQd DQd
K DQd DQd
L DQd DQd
M DQd DQd
N DQPd NC
P NC NC
R MODE NC
/CE
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
/BWc
/BWd
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
5
/BWb
/BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
6
/CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
A1*
A0*
7
/BWE
/GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TDO
TCK
8
/ADSC
/OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
/ADV
/ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
Bottom View
165-Ball, 13 mm x 15mm BGA
PIN DESCRIPTIONS
Symbol
Pin Name
CLK Synchronous Clock
A0,A1
Synchronous Burst Address Inputs
A Address Inputs
/ADV
Synchronous Burst Address Advance
/ADSP
Address Status Processor
/ADSC
Address Status Controller
MODE
Burst Sequence Selection
/CE,CE2,/CE2
Synchronous Chip Enable
/BWE
Byte Write Enable
/BWx (x=a-d)
Synchronous Byte Write Inputs
/GW
Global Write Enable
/OE Output Enable
DQx
Data Inputs/Outputs
DQPx
TCK,TDI,
TDO,TMS
Parity Data I/O
JTAG Pins
ZZ Power Sleep Mode
NC No Connect
VDD
VDDQ
VSS
Power Supply
I/O Power Supply
Ground
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/16/2014
3


3Pages


IS61LPS51236B 電子部品, 半導体
IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
1024K x 18, 119-Ball BGA (Top View)
12
A VDDQ A
B NC A
C NC A
D
DQb
NC
E NC DQb
F
VDDQ
NC
G NC DQb
H
DQb
NC
J
VDDQ
VDD
K NC DQb
L
DQb
NC
M
VDDQ
DQb
N
DQb
NC
P NC DQPb
R NC A
T NC A
U
VDDQ
TMS
3
A
A
A
VSS
VSS
VSS
/BWb
VSS
NC
VSS
VSS
VSS
VSS
VSS
MODE
A
TDI
4
/ADSP
/ADSC
VDD
NC
/CE
/OE
/ADV
/GW
VDD
CLK
NC
/BWE
A1*
A0*
VDD
NC
TCK
5
A
A
A
VSS
VSS
VSS
VSS
VSS
NC
VSS
/BWa
VSS
VSS
VSS
NC
A
TDO
6
A
A
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
A
NC
7
VDDQ
NC
NC
NC
DQa
VDDQ
DQa
NC
VDDQ
DQa
NC
VDDQ
NC
DQa
NC
ZZ
VDDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
Bottom View
119-Ball, 14 mm x 22 mm BGA
PIN DESCRIPTIONS
Symbol
Pin Name
CLK Synchronous Clock
A0,A1
Synchronous Burst Address Inputs
A Address Inputs
/ADV
Synchronous Burst Address Advance
/ADSP
Address Status Processor
/ADSC
Address Status Controller
MODE
Burst Sequence Selection
/CE Synchronous Chip Enable
/BWE
Byte Write Enable
/BWx (x=a-b)
Synchronous Byte Write Inputs
/GW
Global Write Enable
/OE Output Enable
DQx
Data Inputs/Outputs
DQPx
TCK,TDI,
TDO,TMS
ZZ
Parity Data I/O
JTAG Pins
Power Sleep Mode
NC No Connect
VDD
VDDQ
VSS
Power Supply
I/O Power Supply
Ground
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/16/2014
6

6 Page



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[ IS61LPS51236B データシート.PDF ]


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共有リンク

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部品番号部品説明メーカ
IS61LPS51236A

SINGLE CYCLE DESELECT STATIC RAM

Integrated Silicon Solution
Integrated Silicon Solution
IS61LPS51236B

SINGLE CYCLE DESELECT STATIC RAM

Integrated Silicon Solution
Integrated Silicon Solution


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