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54HC190 の電気的特性と機能

54HC190のメーカーはNational Semiconductorです、この部品の機能は「Synchronous Decade Up/Down Counters」です。


製品の詳細 ( Datasheet PDF )

部品番号 54HC190
部品説明 Synchronous Decade Up/Down Counters
メーカ National Semiconductor
ロゴ National Semiconductor ロゴ 




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54HC190 Datasheet, 54HC190 PDF,ピン配置, 機能
January 1988
MM54HC190 MM74HC190 Synchronous
Decade Up Down Counters with Mode
Control MM54HC191 MM74HC191
Synchronous Binary Up Down Counters
with Mode Control
General Description
These high speed synchronous counters utilize advanced
silicon-gate CMOS technology They possess the high noise
immunity and low power consumption of CMOS technology
along with the speeds of low power Schottky TTL
These circuits are synchronous reversible up down count-
ers The MM54HC191 MM74HC191 are 4-bit binary count-
ers and the MM54HC190 MM74HC190 are BCD counters
Synchronous operation is provided by having all flip-flops
clocked simultaneously so that the outputs change simulta-
neously when so instructed by the steering logic This mode
of operation eliminates the output counting spikes normally
associated with asynchronous (ripple clock) counters
The outputs of the four master-slave flip-flops are triggered
on a low-to-high level transition of the clock input if the
enable input is low A high at the enable input inhibits count-
ing The direction of the count is determined by the level of
the down up input When low the counter counts up and
when high it counts down
These counters are fully programmable that is the outputs
may be preset to either level by placing a low on the load
input and entering the desired data at the data inputs The
output will change independent of the level of the clock in-
put This feature allows the counters to be used as modulo-
N dividers by simply modifying the count length with the
preset inputs
Two outputs have been made available to perform the cas-
cading function ripple clock and maximum minimum count
The latter output produces a high-level output pulse with a
duration approximately equal to one complete cycle of the
clock when the counter overflows or underflows The ripple
clock output produces a low-level output pulse equal in
width to the low-level portion of the clock input when an
overflow or underflow condition exists The counters can be
easily cascaded by feeding the ripple clock output to the
enable input of the succeeding counter if parallel clocking is
used or to the clock input if parallel enabling is used The
maximum minimum count output can be used to accom-
plish look-ahead for high-speed operation
Features
Y Level changes on Enable or Down Up can be made re-
gardless of the level of the clock input
Y Wide power supply range 2 – 6V
Y Low quiescent supply current 80 mA maximum
(74HC Series)
Y Low input current 1 mA maximum
Connection Diagram
Dual-In-Line Package
Load
H
H
L
H
Enable
G
L
L
X
H
Down
Up
L
H
X
X
Clock Function
u Count Up
u Count Down
X Load
X No Change
Asynchronous inputs Low input to load sets QA e A
QB e B QC e C and QD e D
Order Number MM54HC190 191 or MM74HC190 191
Top View
C1995 National Semiconductor Corporation TL F 5322
TL F 5322 – 1
RRD-B30M105 Printed in U S A

1 Page





54HC190 pdf, ピン配列
AC Electrical Characteristics TAe25 C VCCe5 0V tretfe6 ns CLe15 pF (unless otherwise specified)
Symbol
Parameter
From
(Input)
To
(Output)
Typ Units
fMAX
Maximum Clock
Frequency
MHz
tPLH tPHL
tPLH tPHL
tPLH tPHL
Maximum Propagation Delay Time
Maximum Propagation Delay Time
Maximum Propagation Delay Time
Load
Data A
BCD
Clock
QA QB
QC QD
QA QB
QC QD
Ripple
Clock
ns
ns
ns
tPLH tPHL
tPLH tPHL
tPLH tPHL
Maximum Propagation Delay Time
Maximum Propagation Delay Time
Maximum Propagation Delay Time
Clock
Clock
Down Up
QA QB
QC QD
Max Min
Ripple
Clock
ns
ns
ns
tPLH tPHL
tPHL tPLH
tW
Maximum Propagation Delay Time
Maximum Propagation Delay Time
Minimum Clock Clear or Load
Input Pulse Width
Down Up
Enable
Max Min
Ripple Clock
ns
ns
ns
AC Electrical Characteristics VCCe2 0V to 6 0V CLe50 pF tretfe6 ns (unless otherwise specified)
Symbol
Parameter
From
To
(Input) (Output) VCC
TAe25 C
Typ
74HC
54HC
TAe b40 to 85 C TAeb55 to 125 C
Guaranteed Limits
Units
fMAX
Maximum Clock
Frequency
V
V
V
MHz
MHz
MHz
tPLH tPHL Maximum Propagation Load
Delay Time
QA QB
QC QD
V
V
V
ns
ns
ns
tPLH tPHL Maximum Propagation Data A QA QB
Delay Time
B C D QC QD
V
V
V
ns
ns
ns
tPLH tPHL Maximum Propagation Clock
Delay Time
Ripple
Clock
V
V
V
ns
ns
ns
tPLH tPHL Maximum Propagation Clock
Delay Time
QA QB
QC QD
V
V
V
ns
ns
ns
3


3Pages


54HC190 電子部品, 半導体
Logic Diagrams (Continued)
’HC191 Binary Counters
Pin (16) e VCC Pin (8) e GND
6
TL F 5322 – 3

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
54HC190

Synchronous Decade Up/Down Counters

National Semiconductor
National Semiconductor
54HC190

4 BIT SYNCHRONOUS UP/DOWN COUNTERS

SGS-THOMSON
SGS-THOMSON
54HC191

Synchronous Binary Up/Down Counters

National Semiconductor
National Semiconductor
54HC191

4 BIT SYNCHRONOUS UP/DOWN COUNTERS

SGS-THOMSON
SGS-THOMSON


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