PDF K4N51163QZ Data sheet ( Hoja de datos )

Número de pieza	K4N51163QZ
Descripción	512Mbit gDDR2 SDRAM
Fabricantes	Samsung
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No Preview Available ! K4N51163QZ 512M gDDR2 SDRAM 512Mbit gDDR2 SDRAM 84FBGA with Halogen-Free & Lead-Free (RoHS compliant) Revision 1.3 September 2008 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER- WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL- OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. 1 of 64 Rev 1.3 September 2008 1 page K4N51163QZ 5.0 PACKAGE DIMENSIONS (84 Ball FBGA) 512M gDDR2 SDRAM MOLDING AREA (Datum A) A (Datum B) B C D E F G H J K L M N P R #A1 9.00 ± 0.10 6.40 0.80 1.60 987654321 A # A1 INDEX MARK B 3.20 (0.95) (1.80) 9.00 ± 0.10 84-∅0.45±0.05 ∅0.2 M A B 5 of 64 0.35±0.05 1.10±0.10 Unit : mm Rev 1.3 September 2008 5 Page K4N51163QZ 512M gDDR2 SDRAM 9.4 Timing Parameters by Speed Grade Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL= x DQ and DM input hold time DQ and DM input setup time Control & Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK/CK DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS Write command to first DQS latching transition DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write postamble Write preamble Address and control input hold time Address and control input setup time Read preamble Read postamble Active to active command period (Refer to notes for informations related to this table at the bottom) Symbol - 20 min max - 25 min max Units Notes tAC tDQSCK tCH tCL -350 -300 0.45 0.45 +350 +300 0.55 0.55 -400 -350 0.45 0.45 +400 +350 0.55 0.55 ps ps tCK tCK tHP min(tCL, tCH) x min(tCL, tCH) x tCK 2.0 8.0 2.5 8.0 tDH 125 x 125 x tDS 50 x 50 x ps 20,21 ns 24 ps 15,16, 17 ps 15,16, 17 tIPW tDIPW tHZ tLZ (DQS) 0.6 x 0.35 x x tAC max tAC min tAC max 0.6 0.35 x x x tAC max tAC min tAC max tCK tCK ps ps 27 tLZ(DQ) 2tAC min tAC max 2tAC min tAC max tDQSQ x 280 x 280 tQHS x 380 x 380 tQH tHP - tQHS x tHP - tQHS x tDQSS WL -0.25 WL +0.25 WL -0.25 WL +0.25 ps ps ps ps tCK 27 22 21 tDQSH 0.35 x 0.35 x tCK tDQSL 0.35 x 0.35 x tCK tDSS 0.2 x 0.2 x tCK tDSH 0.2 x 0.2 x tCK tMRD 2 x2 x tCK tWPST 0.4 0.6 0.4 0.6 tCK 19 tWPRE 0.35 x 0.35 x tCK tIH 200 x 250 x ps 14,16, 18 tIS 150 x 175 x ps 14,16, 18 tRPRE 0.9 1.1 0.9 1.1 tCK 28 tRPST 0.4 0.6 0.4 0.6 tCK 28 tRRD 7.5 x 7.5 x ns 12 11 of 64 Rev 1.3 September 2008 11 Page

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