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PDF RT8881A Data sheet ( Hoja de datos )
| Número de pieza | RT8881A | |
| Descripción | Multi-Phase PWM Controller | |
| Fabricantes | Richtek | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de RT8881A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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®
RT8881A
Dual-Channel, Multi-Phase PWM Controller with I2C Interface
for AMD SVI2 CPU Power Supply
General Description
The RT8881A is a multi-phases PWM controller. Moreover,
it is compliant with AMD SVI2 Voltage Regulator
Specification to support both CPU core (VDD) and
Northbridge portion (VDDNB) of the CPU. The RT8881A
adopts the G-NAVPTM (Green-Native AVP), which is a
Richtek's proprietary topology. The G-NAVP makes it an
easy setting controller to meet all AMD AVP (Adaptive
Voltage Positioning) requirements. The droop is easily
programmed by setting the DC gain of the error amplifier.
With proper compensation, the load transient response
can achieve optimized AVP performance. The RT8881A
uses SVI2 interface to control 8-bit DAC to set output
voltage and operation mode, and support a dynamic
platform master. An I2C interface is available for advanced
power configuration and monitoring. The RT8881A also
features programmable power states with different sets of
operating phase number, over clocking offset, switching
frequency, load-line and protection setting. The platform
master can optimize the performance and efficiency of the
power according to different working scenarios via the I2C
interface. The RT8881A also provides power good
indication, over-current indication and dual OCP
mechanism for AMD SVI2 CPU core and NB. It also
features complete fault protection functions including over-
voltage, under-voltage and negative-voltage protections.
Features
Dual Outputs :
4/3/2/1-Phase for VDD
2/1/0-Phase for VDDNB
G-NAVPTM Topology
Support Dynamic Load-Line and Zero Load-Line
Diode Emulation Mode at Light Load Condition
SVI2 Interface to Comply with AMD Power
Management Protocol
I2C Interface for Platform Configuration
Build-in ADC for VOUT and IOUT Reporting
Immediate OV, UV and NV Protections and UVLO
Programmable Dual OCP Mechanism
Accurate Current Balance
Fast Transient Response
Dynamic Phase Up/Down Control
Programmable Power State Control
Power Good Indicator
Over-Current Indicator
Over Clocking Offset Capabilities
52-Lead WQFN Package
RoHS Compliant and Halogen Free
Applications
AMD SVI2 CPU
Desktop Computer
Simplified Application Circuit
To CPU
To SMBUS
RT8881A
OCP_L PHASE1
SVC
PHASE2
SVD
PWM3
SVT
PWM4
SCL
PWMA1
SDA
PWMA2
MOSFET
MOSFET
RT9624A MOSFET
RT9624A MOSFET
RT9624A MOSFET
RT9624A MOSFET
VVDD
VVDDNB
Copyright ©2014 Richtek Technology Corporation. All rights reserved.
DS8881A-01 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
1 page  
Function Block Diagram
RT8881A
IBIAS
FBA
COMPA
ISENA1P
ISENA1N
ISENA2P
ISENA2N
IMONA
RGND
FB
COMP
ISEN1P
ISEN1N
ISEN2P
ISEN2N
ISEN3P
ISEN3N
ISEN4P
ISEN4N
QR
SEN
QR
SENA
MUX
UVLO
QR QRA
From Control Logic
ADC
I2C/SVI2 Interface
Configuration Registers
Control Logic
OFS/OFSA
Load Line
/Load Line A
RSET/RSETA
Loop Control
Protection Logic
RGND
DAC
Soft-Start & Slew
Rate Control
VSETA
ERROR
AMP
+x 1
-
Offset
Cancellation
Current mirror
+x 1
-
IBA1
V064
+1/3
-
Current mirror
+x 1
IBA2
Average
IMONAI
-
OCP Threshold
PWM
CMPA
+
+-
RSETA
QRA
TONA
TON
GENA
Current Balance
IBA1 IBA2
From Control Logic
OCP_TDCA,
OCP_SPIKEA
+ OCA To Protection Logic
-
DAC
Soft-Start & Slew Rate
Control
ERROR
VSET AMP
+
-
Offset
Cancellation
Current mirror
x+ 1 IB1
-
Current mirror
x+ 1 IB2
-
Current mirror
+x 1 IB3
-
+1/3
-
Average
IMONI
VSENA
OV/UV/NV
PWM
CMP
+
+-
QR
TON
TON
GEN
PWM1
2-PH
PWM2 Driver
RSET
Current Balance
IB1 IB2 IB3 IB4
Current mirror
+x 1 IB4
-
OCP_TDC, +
OCP_SPIKE -
OC To Protection Logic
VSEN OV/UV/NV
GND
TONSETA
PWMA1
PWMA2
TONSET
BOOTx
UGATEx
PHASEx
LGATEx
PWM3
PWM4
IMON V064
Copyright ©2014 Richtek Technology Corporation. All rights reserved.
DS8881A-01 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
5 Page 
Table 4. SET2 Pin Setting
SET2 Pin Voltage
Before Current Injection VSET2 (mV)
34 to 85
110 to 160
235 to 285
310 to 360
435 to 485
510 to 560
636 to 686
711 to 761
836 to 886
911 to 961
1036 to 1086
1112 to 1162
1237 to 1287
1312 to 1362
1437 to 1487
1512 to 1562
QRTH
(for VDD)
Disable
Disable
30mV
35mV
40mV
45mV
50mV
55mV
RT8881A
OCPTRGDELAY
(for VDD/VDDNB)
10ms
40ms
10ms
40ms
10ms
40ms
10ms
40ms
10ms
40ms
10ms
40ms
10ms
40ms
10ms
40ms
Table 5. Quick Response Threshold for VDDNB Controller
SET2 Pin Voltage Difference VSET2
(Before and After Current Injection) (mV)
QRTHA (for VDDNB)
19 Disable
72 Disable
122 30mV
172 35mV
222 40mV
272 45mV
323 50mV
373 55mV
Copyright ©2014 Richtek Technology Corporation. All rights reserved.
DS8881A-01 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet RT8881A.PDF ] | |
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