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RT8878A の電気的特性と機能

RT8878AのメーカーはRichtekです、この部品の機能は「Dual-Output PWM Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 RT8878A
部品説明 Dual-Output PWM Controller
メーカ Richtek
ロゴ Richtek ロゴ 




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RT8878A Datasheet, RT8878A PDF,ピン配置, 機能
®
RT8878A
Dual-Output PWM Controller with 2 Integrated Drivers for
AMD SVI2 CPU Power Supply
General Description
The RT8878A is a 4 + 2 phases PWM controller, and is
compliant with AMD SVI2 Voltage Regulator Specification
to support both CPU core (VDD) and Northbridge portion
of the CPU (VDDNB). The RT8878A features CCRCOT
(Constant Current Ripple Constant On-Time) with G-NAVP
(Green-Native AVP), which is Richtek's proprietary
topology. G-NAVP makes it an easy setting controller to
meet all AMD AVP (Active Voltage Positioning) VDD/
VDDNB requirements. The droop is easily programmed
by setting the DC gain of the error amplifier. With proper
compensation, the load transient response can achieve
optimized AVP performance. The controller also uses the
interface to issue VOTF Complete and to send digitally
encoded voltage and current values for the VDD and
VDDNB domains. It can operate in single phase and diode
emulation mode and reach up to 90% efficiency in different
modes according to different loading conditions. The
RT8878A provides special purpose offset capabilities by
pin setting. The RT8878A also provides power good
indication, over current indication (OCP_L) and dual OCP
mechanism for AMD SVI2 CPU core and NB. It also
features complete fault protection functions including over
voltage, under voltage and negative voltage.
Features
4/3/2/1-Phase (VDD) + 2/1/0-Phase (VDDNB) PWM
Controller
2 Embedded MOSFET Drivers at the VDD Controller
G-NAVPTM Topology
Support Dynamic Load-Line and Zero Load-Line
Diode Emulation Mode at Light Load Condition
SVI2 Interface to Comply AMD Power Management
Protocol
Build-in ADC for VOUT and IOUT Reporting
Immediate OV, UV and NV Protections and UVLO
Programmable Dual OCP Mechanism
0.5% DAC Accuracy
Fast Transient Response
Power Good Indicator
Over Current Indicator
52-Lead WQFN Package
RoHS Compliant and Halogen Free
Applications
AMD SVI2 CPU
Desktop Computer
Simplified Application Circuit
To CPU
RT8878A
OCP_L PHASE1
SVC
PHASE2
PWM3
SVD
PWM4
PWMA1
SVT PWMA2
MOSFET
MOSFET
RT9624A MOSFET
RT9624A MOSFET
RT9624A MOSFET
RT9624A MOSFET
VVDD
VVDDNB
Copyright ©2014 Richtek Technology Corporation. All rights reserved.
DS8878A-01 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1

1 Page





RT8878A pdf, ピン配列
RT8878A
Functional Pin Description
Pin No.
1, 52
2
5, 4, 8, 9
Pin Name
PWM4, PWM3
TONSET
ISEN1N to ISEN4N
Pin Function
PWM Outputs for Channel 3 and 4 of VDD Controller.
VDD Controller On-Time Setting. Connect this pin to the converter input
voltage, VIN, through a resistor, RTON, to set the on-time of UGATE and
also the output voltage ripple of VDD controller.
Negative Current Sense Input of Channel 1, 2, 3 and 4 for VDD Controller.
6, 3, 7, 10 ISEN1P to ISEN4P Positive Current Sense Input of Channel 1, 2, 3 and 4 for VDD Controller.
11 VSEN
VDD Controller Voltage Sense Input. This pin is connected to the terminal
of VDD controller output voltage.
12 FB
Output Voltage Feedback Input of VDD Controller. This pin is the negative
input of the error amplifier for the VDD controller.
13 COMP
14 RGND
15 IMON
16 V064
17 IMONA
18 VDDIO
19 PWROK
Error Amplifier Output Pin of the VDD Controller.
Return Ground of VDD and VDDNB Controller. This pin is the common
negative input of output voltage differential remote sense for VDD and
VDDNB controllers.
Current Monitor Output for the VDD Controller. This pin outputs a voltage
proportional to the output current.
Fixed 0.64V Reference Voltage Output. This voltage is only used to offset
the output voltage of IMON pin and IMONA pin. Connect a 0.47F
capacitor from this pin to GND.
Current Monitor Output for the VDDNB Controller. This pin outputs a
voltage proportional to the output current.
Processor memory interface power rail and serves as the reference for
PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the
SVI pins.
System Power Good Input. If PWROK is low, the SVI interface is disabled
and VR returns to BOOT-VID state with initial load line slope and initial
offset. If PWROK is high, the SVI interface is running and the DAC
decodes the received serial VID codes to determine the output voltage.
20 SVC
Serial VID Clock Input from Processor.
21 SVD
Serial VID Data input from Processor. This pin is a serial data line.
22 SVT
Serial VID Telemetry Input from VR. This pin is a push-pull output.
23 OFS
Over Clocking Offset Setting for the VDD Controller.
24 OFSA
Over Clocking Special Purpose Offset Setting for the VDDNB Controller.
25 SET1
26 SET2
OCP_TDC threshold setting individually for VDD and VDDNB controllers
and also the internal ramp slew rate setting (RSET and RSETA)
individually for VDD and VDDNB controllers.
Quick response threshold setting individually for VDD and VDDNB
controllers (QRTH and QRTHA) and also the OCP_TDC trigger delay time
setting for both controllers and over clocking offset enable setting.
27 OCP_L
Over Current Indicator for Dual OCP Mechanism. This pin is an open drain
output.
28 VCC
Controller Power Supply Input. Connect this pin to 5V with an 1F or
greater ceramic capacitor for decoupling.
Copyright ©2014 Richtek Technology Corporation. All rights reserved.
DS8878A-01 January 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3


3Pages


RT8878A 電子部品, 半導体
RT8878A
Operation
MUX and ADC
The MUX supports the inputs from SET1, SET2, OFS,
OFSA, IMON, IMONA, VSEN, or VSENA. The ADC
converts these analog signals to digital codes for reporting
or performance adjustment.
SVI2 Interface
The SVI2 interface uses the SVC, SVD, and SVT pins to
communicate with CPU. The RT8878A's performance and
behavior can be adjusted by commands sent by CPU or
platform.
UVLO
The UVLO detects VCC pin voltages for under voltage
lockout protection and power on reset operation.
Loop Control Protection Logic
Loop control protection logic detects EN and UVLO signals
to initiate soft-start function and control PGOOD,
PGOODA and OCP_L signals after soft-start is finished.
When dual OCP event occurs, the OCP_L pin voltage will
be pulled low.
DAC
The DAC receives VID codes from the SVI2 control logic
to generate an internal reference voltage (VSET/VSETA)
for controller.
Soft-Start and Slew-Rate Control
This block controls the slew rate of the internal reference
voltage when output voltage changes.
Error Amp
Error amplifier generates COMP/COMPA signal by the
difference between VSET/VSETA and FB/FBA.
Offset cancellation
This block cancels the output offset voltage from voltage
ripple and current ripple to achieve accurate output voltage.
PWM CMPx
The PWM comparator compares COMP signal and current
feedback signal to generate a signal for TONGENx.
TONGEN/TONGENA
This block generates an on-time pulse which high interval
is based on the on-time setting and current balance.
Current Balance
Per-phase current is sensed and adjusted by adjusting
on-time of each phase to achieve current balance for each
phase.
OC/OV/UV/NV
VSEN/VSENA and output current are sensed for over
current, over voltage, under voltage, and negative voltage
protection.
RSET/RSETA
The Ramp generator is designed to improve noise immunity
and reduce jitter.
Copyright ©2014 Richtek Technology Corporation. All rights reserved.
www.richtek.com
6
is a registered trademark of Richtek Technology Corporation.
DS8878A-01 January 2014

6 Page



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共有リンク

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部品番号部品説明メーカ
RT8878A

Dual-Output PWM Controller

Richtek
Richtek
RT8878B

Dual-Output PWM Controller

Richtek
Richtek


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