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RT8179C の電気的特性と機能

RT8179CのメーカーはRichtekです、この部品の機能は「Dual-Output PWM Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 RT8179C
部品説明 Dual-Output PWM Controller
メーカ Richtek
ロゴ Richtek ロゴ 




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RT8179C Datasheet, RT8179C PDF,ピン配置, 機能
®
RT8179C
Dual-Output PWM Controller with 2 Integrated Drivers for
AMD SVI2 Mobile CPU Power Supply
General Description
The RT8179C is a dual-output PWM controller, and is
compliant with AMD SVI2 Voltage Regulator Specification
to support both CPU core (VDD) and Northbridge portion
of the CPU (VDDNB). The RT8179C features CCRCOT
(Constant Current Ripple Constant On-Time) with G-NAVP
(Green-Native AVP), which is Richtek's proprietary
topology. G-NAVP makes it an easy setting controller to
meet all AMD AVP (Adaptive Voltage Positioning) VDD/
VDDNB requirements. The droop is easily programmed
by setting the DC gain of the error amplifier. With proper
compensation, the load transient response can achieve
optimized AVP performance. The controller also uses the
interface to issue VOTF Complete and to send digitally
encoded voltage and current values for the VDD and
VDDNB domains. It can operate in diode emulation mode
and reach up to 90% efficiency in different modes according
to different loading conditions. The RT8179C provides
special purpose offset capabilities by pin setting. The
RT8179C also provides power good indication, over
current indication (OCP_L) and dual OCP mechanism for
AMD SVI2 CPU core and NB. It also features complete
fault protection functions including over voltage, under
voltage and negative voltage.
Features
1-Phase (VDD) + 1/0-Phase (VDDNB) PWM Controller
2 Embedded MOSFET Drivers
G-NAVPTM Topology
Support Dynamic Load-Line and Zero Load-Line
Diode Emulation Mode at Light Load Condition
SVI2 Interface to Comply with AMD Power
Management Protocol
Build-in ADC for VOUT and IOUT Reporting
Immediate OV, UV and NV Protections and UVLO
Programmable Dual OCP Mechanisms
DVID Turbo Boost Compensation
0.5% DAC Accuracy
Fast Transient Response
Power Good Indicator
Over Current Indicator
RoHS Compliant and Halogen Free
Applications
AMD SVI2 Mobile CPU
Laptop Computer
Simplified Application Circuit
To CPU
RT8179C
OCP_L
PHASE
SVC
MOSFET
SVD
SVT
PHASEA MOSFET
VVDD
VVDDNB
Copyright ©2015 Richtek Technology Corporation. All rights reserved.
DS8179C-01 January 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1

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RT8179C pdf, ピン配列
RT8179C
Functional Pin Description
Pin No.
Pin Name
Pin Function
1, 33
BOOT,
BOOTA
Bootstrap Supply for High Side MOSFET. This pin powers high side MOSFET
driver.
VDD Controller On-Time Setting. Connect this pin to the converter input
2
TONSET
voltage, VIN, through a resistor, RTON, to set the on-time of UGATE and also
the output voltage ripple of VDD controller.
4 ISEN1P Positive Current Sense Input of Channel 1 for VDD Controller.
3 ISEN1N Negative Current Sense Input of Channel 1 for VDD Controller.
5 VSEN
VDD Controller Voltage Sense Input. This pin is connected to the terminal of
VDD controller output voltage.
6 FB
Output Voltage Feedback Input of VDD Controller. This pin is the negative input
of the error amplifier for the VDD controller.
7 COMP
8 RGND
9 IMON
Error Amplifier Output Pin of the VDD Controller.
Return Ground of VDD and VDDNB Controller. This pin is the common
negative input of output voltage differential remote sense for VDD and VDDNB
controllers.
Current Monitor Output for the VDD Controller. This pin outputs a voltage
proportional to the output current.
10 V064
Fixed 0.64V Output Reference Voltage Output. This voltage is only used to
offset the output voltage of the IMON pin and the IMONA pin. Connect a 0.47F
capacitor from this pin to GND.
11 IMONA
Current Monitor Output for the VDDNB Controller. This pin outputs a voltage
proportional to the output current.
12 VDDIO
Processor Memory Interface Power Rail and Serves as the Reference for
PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the SVI
pins.
System Power Good Input. If PWROK is low, the SVI interface is disabled and
13
PWROK
VR returns to BOOT-VID state with initial load-line slope and initial offset. If
PWROK is high, the SVI interface is running and the DAC decodes the
received serial VID codes to determine the output voltage.
14 SVC
Serial VID Clock Input from Processor.
15 SVD
Serial VID Data Input from Processor. This pin is a serial data line.
16 SVT
Serial VID Telemetry Input from VR. This pin is a push-pull output.
17 OFS
Over Clocking Offset Setting for the VDD Controller.
18 OFSA
Over Clocking Offset Setting for the VDDNB Controller.
19 SET1
1st Platform Setting Pin. Platform can use this pin to set OCP_TDC threshold,
DVID compensation bit1 and internal ramp slew rate.
20 SET2
2st Platform Setting Pin. Platform can use this pin to set quick response
threshold, OCP_TDC trigger delay time, DVID compensation bit0, VDDNB rail
zero load-line enable setting and over clocking offset enable setting.
21 OCP_L
Over Current Indicator for Dual OCP Mechanism. This pin is an open drain
output.
22 VCC
Controller Power Supply Input. Connect this pin to 5V with an 1F or greater
ceramic capacitor for decoupling.
Copyright ©2015 Richtek Technology Corporation. All rights reserved.
DS8179C-01 January 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3


3Pages


RT8179C 電子部品, 半導体
RT8179C
Operation
MUX and ADC
The MUX supports the inputs from SET1, SET2, OFS,
OFSA, IMONI, IMONAI, VSEN, or VSENA. The ADC
converts these analog signals to digital codes for reporting
or performance adjustment.
SVI2 Interface
The SVI2 interface uses the SVC, SVD, and SVT pins to
communicate with CPU. The RT8179C's performance and
behavior can be adjusted by commands sent by CPU or
platform.
UVLO
The UVLO detects the VCC pin voltages for under voltage
lockout protection and power on reset operation.
Loop Control Protection Logic
Loop control protection logic detects EN and UVLO signals
to initiate soft-start function and control PGOOD,
PGOODA and OCP_L signals after soft-start is finished.
When dual OCP event occurs, the OCP_L pin voltage will
be pulled low.
DAC
The DAC receives VID codes from the SVI2 control logic
to generate an internal reference voltage (VSET/VSETA)
for controller.
Soft-Start and Slew-Rate Control
This block controls the slew rate of the internal reference
voltage when output voltage changes.
Error Amplifier
Error amplifier generates COMP/COMPA signal by the
difference between VSET/VSETA and FB/FBA.
Offset Cancellation
This block cancels the output offset voltage from voltage
ripple and current ripple to achieve accurate output voltage.
PWM CMPx
The PWM comparator compares COMP signal and current
feedback signal to generate a signal for TONGENx.
TONGEN/TONGENA
This block generates an on-time pulse which high interval
is based on the on-time setting and current balance.
OC/OV/UV/NV
VSEN/VSENA and output current are sensed for over
current, over voltage, under voltage, and negative voltage
protection.
RSET/RSETA
The Ramp generator is designed to improve noise immunity
and reduce jitter.
Copyright ©2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
6
is a registered trademark of Richtek Technology Corporation.
DS8179C-01 January 2015

6 Page



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共有リンク

Link :


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