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Datasheet RT3606BC PDF ( 特性, スペック, ピン接続図 )

部品番号 RT3606BC
部品説明 Dual Channel PWM Controller
メーカ RichTek
ロゴ RichTek ロゴ 
プレビュー
Total 30 pages
		
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RT3606BC Datasheet, RT3606BC PDF,ピン配置, 機能
®
RT3606BC
Dual Channel PWM Controller with Integrated Driver for IMVP8
CPU Core Power Supply
General Description
Features
The RT3606BC is an IMVP8 compliant CPU power
controller which includes two voltage rails : a 3/2/1 phase
synchronous Buck controller, the CORE VR and a 2/1
phase synchronous Buck controller, the AXG VR. The
RT3606BC adopts G-NAVPTM (Green Native AVP) which
is Richtek's proprietary topology derived from finite DC
gain of EA amplifier with current mode control, making it
easy to set the droop to meet all Intel CPU requirements
of AVP (Adaptive Voltage Positioning). Based on the G-
NAVPTM topology, the RT3606BC also features a quick
response mechanism for optimized AVP performance
during load transient. The RT3606BC supports mode
transition function with various operating states. A serial
VID (SVID) interface is built in the RT3606BC to
communicate with Intel IMVP8 compliant CPU. The
RT3606BC supports VID on-the-fly function with three
different slew rates : Fast, Slow and Decay. By utilizing
the G-NAVPTM topology, the operating frequency of the
RT3606BC varies with VID, load and input voltage to further
enhance the efficiency even in CCM. Moreover, the G-
NAVPTM with CCRCOT (Constant Current Ripple COT)
technology provides superior output voltage ripple over
the entire input/output range. The built-in high accuracy
DAC converts the SVID code ranging from 0.25V to 1.52V
with 5mV per step. The RT3606BC integrates a high
accuracy ADC for platform setting functions, such as quick
response trigger level or over-current level. Besides, the
setting function also supports this two rails address
exchange. The RT3606BC provides VR ready output
signals. It also features complete fault protection functions
including over-voltage (OV), negative voltage (NV), over-
current (OC) and under-voltage lockout (UVLO). The
RT3606BC is available in the WQFN-60L 7x7 small foot
print package.
Intel IMVP8 Serial VID Interface Compatible Power
Management States
3/2/1 Phase (CORE VR) + 2/1 Phase (AXG VR) PWM
Controller
2 Embedded MOSFET Drivers at the CORE VR, 1
Embedded MOSFET Driver at the AXG VR
G-NAVPTM (Green Native Adaptive Voltage
Positioning) Topology
0.5% DAC Accuracy
Differential Remote Voltage Sensing
Built-in ADC for Platform Programming
Accurate Current Balance
System Thermal Compensated AVP
Diode Emulation Mode at Light Load Condition for
Single Phase Operation
Fast Transient Response
VR Ready Indicator
Thermal Throttling
Current Monitor Output
OVP, OCP, NVP, UVLO
Slew Rate Setting/Address Flip Function
Rail Address Flexibility
DVID Enhancement
Applications
IMVP8 Intel Core Supply
Notebook/ Desktop Computer/ Servers Multi-phase CPU
Core Supply
AVP Step-Down Converter
Simplified Application Circuit
To PCH
To CPU
RT3606BC
PGOOD PHASE1
VR_HOT PHASE2
VCLK
PWM3
VDIO PHASEA1
ALERT PWMA2
Driver
Driver
MOSFET
MOSFET
MOSFET
MOSFET
MOSFET
VCORE
VAXG
Copyright ©2016 Richtek Technology Corporation. All rights reserved.
DS3606BC-04 June 2016
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1

1 Page



RT3606BC pdf, ピン配列
RT3606BC
Pin No
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31, 39, 46
32
33
34
35
36
40, 38
41, 37
42
43
44
Pin Name
SET3
SETA1
Pin Function
3rd Platform setting. Platform can use this pin to set VR address, Zero load-line, Anti-
overshoot function and behavior, AI gain, Disable DVID compensation, Decrease
GTU and SA ramp (only in maximum phase = 1-phase), high frequency ramp, DVID
slew rate, and PSYS function for CORE VR and AXG VR.
1st Platform Setting. Platform can use this pin to set OCS, DVID threshold and
ICCMAX for AXG rail VR.
SETA2
2nd Platform Setting. Platform can use this pin to set RSET, QRTH, QRWIDTH and
DVID width for AXG rail VR.
IMON
CORE rail VR Current Monitor Output. This pin outputs a voltage proportional to the
loading current.
VREF
Fixed 0.6V Output Reference Voltage. This voltage is only used to offset the output
voltage of IMON pin. Between this pin and GND must be placed a RC circuit with R
= 1and C = 0.47F.
IMONA
AXG rail VR Current Monitor Output. This pin outputs a voltage proportional to the
loading current.
VR_HOT Thermal Monitor Output, this Pin is Active Low.
ALERT
SVID Alert. (Active low)
VDIO
VR and CPU Data Transmission Interface.
VCLK
Synchronous Clock from the CPU.
EN VR Enable Control Input.
OFSM
Output Voltage Offset Setting for CORE rail VR.
OFSA/PSYS
Output Voltage Offset Setting for AXG rail VR / System Input Power Monitor. Place
the PSYS resistor as close to the IC as possible.
VCC
Controller Power Supply. Connect this pin to 5V and place a decoupling capacitor
2.2F at least. The decoupling capacitor is placed as close VR controller as possible.
NC No Internal Connection.
IBIAS
Internal Bias Current Setting. Connect a 100kresistor from this pin tied to GND to
set the internal current. Don’t connect a bypass pass capacitor from this pin to GND.
RGNDA
Return Ground for AXG rail VR. This pin is the negative node of the differential
remote voltage sensing.
VSENA
AXG rail VR Voltage Sense Input. This pin is connected to the terminal of AXG rail
VR output voltage.
COMPA
AXG rail VR Compensation. This pin is the error amplifier output pin.
FBA
Negative Input of the Error Amplifier. This pin is for AXG rail VR output voltage
feedback to controller.
ISENA[1:2]P Positive Current Sense Input of Multi-Phase AXG rail VR Channel 1, 2.
ISENA[1:2]N Negative Current Sense Input of Multi-Phase AXG rail VR Channel 1, 2.
TSENA
Thermal Sense Input for AXG rail VR.
TONSETA
AXG rail VR On-time Setting. An on-time setting resistor is connected from this pin
to input voltage.
DVD
Divided Input Voltage Detection of Power Stage. Connect this pin to a voltage divider
from input voltage of power stage to detect input voltage.
Copyright ©2016 Richtek Technology Corporation. All rights reserved.
DS3606BC-04 June 2016
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3


3Pages


RT3606BC 電子部品, 半導体
RT3606BC
Operation
The RT3606BC adopts G-NAVPTM (Green Native AVP)
which is Richtek's proprietary topology derived from finite
DC gain of EA amplifier with current mode control, making
it easy to set the droop to meet all Intel CPU requirements
of AVP (Adaptive Voltage Positioning).
The G-NAVPTM controller is one type of current mode
constant on-time control with DC offset cancellation. The
approach can not only improve DC offset problem for
increasing system accuracy but also provide fast transient
response. When current feedback signal reaches COMP
signal, the RT3606BC generates an on-time width to
achieve PWM modulation.
TON GEN/Driver Interface
Generate the PWM1 to PWM3 sequentially according to
the phase control signal from the Loop Control/Protection
Logic. Pulse width is determined by current balance result
and TONSET pin setting. Once quick response mechanism
is triggered, VR will allow all PWM to turn on at the same
time. PWM status is also controlled by Protection Logic.
Different protections may cause different PWM status
(Both High-Z or LG turn-on).
SVID Interface/Configuration Registers/Control
Logic
The interface receives the SVID signal from CPU and sends
the relative signals to Loop Control/Protection Logic for
loop control to execute the action by CPU. The registers
save the pin setting data from ADC output. The Control
Logic controls the ADC timing and generates the digital
code of the VID for VSEN voltage.
Loop Control/Protection Logic
It controls the power on sequence, the protection behavior,
and the operational phase number.
MUX and ADC
The MUX supports the inputs from SET1, SET2, SET3,
SETA1, SETA2, IMONI_M, IMONI_A, TSEN or TSENA.
The ADC converts these analog signals to digital codes
for reporting or performance adjustment.
Current Balance
Each phase current sense signal is sent to the current
balance circuit which adjusts the on-time of each phase
to optimize current sharing.
Offset Cancellation
Cancel the current/voltage ripple issue to get the accurate
VSEN.
UVLO
Detect the DVD and VCC voltage and issue POR signal as
they are high enough.
DAC
Generate an analog signal according to the digital code
generated by Control Logic.
Soft-Start & Slew Rate Control
Control the Dynamic VID slew rate of DAC according to
the SetVID fast or SetVID slow.
Error Amp
Error amplifier generates COMP/COMPA signal by the
difference between VSEN/VSENA and FB/FBA.
RSET/RSETA
The Ramp generator is designed to improve noise immunity
and reduce jitter.
PWM CMP
The PWM comparator compares COMP signal and current
feedback signal to generate a signal for TON trigger.
IMON Filter
IMON Filter is used to average sum current signal by
analog RC filter.
Copyright ©2016 Richtek Technology Corporation. All rights reserved.
www.richtek.com
6
is a registered trademark of Richtek Technology Corporation.
DS3606BC-04 June 2016

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