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PDF RT3662AC Data sheet ( Hoja de datos )

Número de pieza RT3662AC
Descripción Dual-Output PWM Controller
Fabricantes RichTek 
Logotipo RichTek Logotipo



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No Preview Available ! RT3662AC Hoja de datos, Descripción, Manual

RT3662AC
Dual-Output PWM Controller with 3 Integrated Drivers for
AMD SVI2 Mobile CPU Power Supply
General Description
RT3662AC is a dual-output PWM controller with 3
integrated drivers, and it is compliant with AMD SVI2
Voltage Regulator Specification to support both CPU
core (VDD) and Northbridge portion of CPU (VDDNB).
The RT3662AC features CCRCOT (Constant Current
Ripple Constant On-Time) with G-NAVP (Green-Native
AVP), which is Richtek's proprietary topology. G-NAVP
makes it an easy setting controller to meet all AMD AVP
(Adaptive Voltage Positioning) VDD/VDDNB
requirements. The droop is easily programmed by
setting the DC gain of the error amplifier. With proper
compensation, the load transient response can achieve
optimized AVP performance. The controller also uses
the interface to issue VOTF Complete and to send
digitally encoded voltage and current values for the
VDD/VDDNB domains. The RT3662AC can operate in
diode emulation mode to enhance the light load
efficiency. And it provides the current gain adjustment
capability by pin setting. RT3662AC provides power
good indication, thermal indication (VRHOT_L), and it
features complete fault protection functions including
over current, over voltage and under voltage.
Marking Information
RT3662AC
GQW
YMDNN
RT3662ACGQW : Product Number
YMDNN : Date Code
Features
2/1-Phase (VDD) + 1/0-Phase (VDDNB) PWM
Controller
3 Embedded MOSFET Drivers
G-NAVPTM Topology
Support Dynamic Load-Line and Zero Load-Line
Diode Emulation Mode at Light Load Condition
SVI2 Interface to Comply with AMD Power
Management Protocol
Adjustable Current Gain Capability
DVID Enhancement
0.5% DAC Accuracy
Differential Remote Voltage Sensing
Build-in ADC for Pin Setting Programming,
Thermal Indication and VOUT, IOUT Reporting
Fast Transient Response
Power Good Indicator
Thermal Indicator (VRHOT_L)
OVP, UVP and UVLO
Over Current Protection
Applications
AMD SVI2 Mobile CPU
Laptop Computer
Simplified Application Circuit
To CPU
RT3662AC
VRHOT_L
PHASE1
SVC
SVD
PHASE2
SVT
PHASE_NB
MOSFET
MOSFET
MOSFET
VVDD
VVDDNB
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
DS3662AC-01 April 2016
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1

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RT3662AC pdf
Function Block Diagram
RT3662AC
UVLO
RGND
FB
COMP
ISEN1P
ISEN1N
ISEN2P
IMON
VREF_PINSET
FB_NB
COMP_NB
ISENP_NB
ISENN_NB
IMON_NB
From Control Logic
MUX
ADC
DAC
Soft Start&
Slew Rate Control
VSET
ERROR
+ AMP
-
SVI2 Interface
Configuration Registers
Control Logic
Offset
Cancellation
1.867m
+ IB1
-
1.867m
+ IB2
-
0.75 x AI_VDD
+
-
IMONI
From Control Logic
RGND
DAC
OCP_SPIKE
+ OC
-
Soft Start&
Slew Rate Control
ERROR
VSET_NB AMP
+
-
Offset
Cancellation
1.867m
+
-
0.75 x AI_VDDNB
VREF_PINSET
+
-
IMONI_NB
AI_VDD, AI_VDDNB
QR_TH
TONSET
OFFSET
PHOCP_TH
VDDNB Voltage
Reporting Compensation
Loop Control
Protection
Logic
+
RAMP
+
- PWM
CMP
QR_TH
TONSET
TON
GEN
PWM1
PWM2 Driver
VSEN
OV/UV
Current
Balance
IB1 IB2
Driver
POR
To Protection Logic
PWM
+ CMP
+-
RAMP
TONSET
VIN
TON
GEN
PWM
_NB
Driver
ISENN_NB
OCP_SPIKE_NB
+ OC_NB
-
OV/UV
To Protection Logic
GND
VIN
BOOTx
UGATEx
PHASEx
LGATEx
PVCC
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
DS3662AC-01 April 2016
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5

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RT3662AC arduino
RT3662AC
Table 5. TSEN_NB Pin Setting for VDDNB Controller Initial Offset, Voltage Reporting Offset and PHOCP
Setting Ratio
TSEN_NB Pin Setting Voltage
VTSEN_NB_DIV
3.2RD
RU RD
Min
Typical
Max
Unit
0 23 47 mV
50 74 97 mV
100 124 147 mV
150 174 197 mV
200 224 247 mV
250 274 297 mV
300 324 347 mV
350 374 397 mV
400 424 447 mV
450 474 497 mV
500 524 547 mV
551 574 597 mV
601 624 648 mV
651 674 698 mV
701 724 748 mV
751 774 798 mV
801 824 848 mV
851 874 898 mV
901 924 948 mV
951 974 998 mV
1001
1024
1048
mV
1051
1074
1098
mV
1101
1125
1148
mV
1151
1175
1198
mV
1201
1225
1248
mV
1251
1275
1298
mV
1301
1325
1348
mV
1351
1375
1398
mV
1401
1425
1448
mV
1451
1475
1498
mV
1501
1525
1548
mV
1552
1575
1598
mV
Initial Offset VDDNB_RPT
(VDDNB)
_OFS [0]
25mV
(PS0)
0mV
(PS0)
25mV
(PS0)
50mV
(PS0)
Fixed 1.5V
(PS2)
Fixed 1.35V
(PS2)
Fixed 1.25V
(PS2)
0mV
(PS2)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VDDNB PHOCP
Setting Ratio
(Percentage of
OCP_SPIKE_NB)
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
DS3662AC-01 April 2016
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
11

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