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Datasheet AD9234 PDF ( 特性, スペック, ピン接続図 )

部品番号 AD9234
部品説明 Dual Analog-to-Digital Converter
メーカ Analog Devices
ロゴ Analog Devices ロゴ 
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AD9234 Datasheet, AD9234 PDF,ピン配置, 機能
Data Sheet
12-Bit, 1 GSPS/500 MSPS JESD204B,
Dual Analog-to-Digital Converter
AD9234
FEATURES
JESD204B (Subclass 1) coded serial digital outputs
1.5 W total power per channel at 1 GSPS (default settings)
SFDR
79 dBFS at 340 MHz (1 GSPS)
86 dBFS at 340 MHz (500 MSPS)
SNR
63.4 dBFS at 340 MHz (AIN = −1.0 dBFS, 1 GSPS)
65.6 dBFS at 340 MHz (AIN = −1.0 dBFS, 500 MSPS)
ENOB = 10.4 bits at 10 MHz
DNL = ±0.16 LSB; INL = ±0.35 LSB
Noise density
−151 dBFS/Hz (1 GSPS)
−150 dBFS/Hz (500 MSPS)
1.25 V, 2.5 V, and 3.3 V dc supply operation
Low swing full scale input
1.34 V p-p nominal (1 GSPS)
1.63 V p-p nominal (500 MSPS)
No missing codes
Internal ADC voltage reference
Flexible termination impedance
400 Ω, 200 Ω, 100 Ω, and 50 Ω differential
2 GHz usable analog input full power bandwidth
95 dB channel isolation/crosstalk
Amplitude detect bits for efficient AGC implementation
Differential clock input
Optional decimate-by-2 DDC per channel
Differential clock input
Integer clock divide by 1, 2, 4, or 8
Flexible JESD204B lane configurations
Small signal dither
APPLICATIONS
Communications
Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
Point-to-point radio systems
Digital predistortion observation path
General-purpose software radios
Ultrawideband satellite receiver
Instrumentation (spectrum analyzers, network analyzers,
integrated RF test solutions)
Digital oscilloscopes
High speed data acquisition systems
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD
(1.25V) (2.5V) (3.3V) (1.25V) (1.25V) (1.25V) (1.8V TO 3.3V)
VIN+A
VIN–A
FD_A
FD_B
VIN+B
VIN–B
V_1P0
CLK+
CLK–
BUFFER
ADC
CORE 12
DECIMATE
BY 2
SIGNAL
MONITOR
12
ADC
CORE
DECIMATE
BY 2
BUFFER
CLOCK
GENERATION
AND ADJUST
JESD204B
SUBCLASS 1
CONTROL
4 SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
FAST
DETECT
SYNCINB±
SYSREF±
÷2
÷4
SPI CONTROL
SIGNAL
MONITOR
PDWN/
÷8
AD9234
STBY
AGND DRGND DGND SDIO SCLK CSB
Figure 1.
PRODUCT HIGHLIGHTS
1. Low power consumption analog core, 12-bit, 1.0 GSPS dual
analog-to-digital converter (ADC) with 1.5 W per channel.
2. Wide full power bandwidth supports IF sampling of signals
up to 2 GHz.
3. Buffered inputs with programmable input termination
eases filter design and implementation.
4. Flexible serial port interface (SPI) controls various product
features and functions to meet specific system requirements.
5. Programmable fast overrange detection.
6. 9 mm × 9 mm 64-lead LFCSP.
7. Pin compatible with the AD9680 14-bit, 1 GSPS/500 MSPS
dual ADC.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 Page



AD9234 pdf, ピン配列
Data Sheet
REVISION HISTORY
3/15—Rev. 0 to Rev. A
Added AD9234-500 ........................................................... Universal
Changes to Features Section ............................................................1
Changes to Table 1 ............................................................................5
Changes to Table 2 ............................................................................6
Changes to Table 4 ............................................................................9
Changes to Table 6, Thermal Characteristics Section, and
Table 7 ...............................................................................................11
Added AD9234-500 Section and Figure 29 to Figure 51...........18
Changes to Figure 63 and Figure 64 Captions, Analog Input
Controls and SFDR Optimization Section, and Figure 66 ........25
Changes to Figure 70 and Figure 71...............................................26
Changes to Voltage Referece Section..............................................27
AD9234
Changes to Figure 79 ......................................................................28
Changes to Figure 80 ......................................................................29
Changes to Figure 91 ......................................................................38
Changes to DDC General Description Section ..........................34
Added Example 2: Full Bandwidth Mode at 500 MSPS Section...44
Added Test Modes Section and Table 15 to Table 19 .................50
Changes to Table 22 ........................................................................55
Changes to Power Supply Recommendations Section and
Figure 106.........................................................................................65
Changes to Ordering Guide...........................................................66
8/14—Revision 0: Initial Version
Rev. A | Page 3 of 66


3Pages


AD9234 電子部品, 半導体
AD9234
Data Sheet
Parameter
POWER CONSUMPTION
Total Power Dissipation (Including Output Drivers)2
Total Power Dissipation (L = 2 Mode)
Power-Down Dissipation
Standby4
Temp
AD9234-500
Min Typ Max
AD9234-1000
Min Typ Max
Full 2.15 2.5
25°C 2.08
Full 670
Full 1.1
3.0
N/A3
750
1.25
3.3
Unit
W
W
mW
W
1 All lanes running. Power dissipation on DRVDD changes with lane rate and number of lanes used.
2 Default mode. No DDCs used. L = 4, M = 2, F = 1.
3 N/A = not applicable. At the maximum sample rate, it is not applicable to use L = 2 mode on the JESD204B output interface because this exceeds the maximum lane
rate of 12.5 Gbps. L = 2 mode is supported when the equation ((M × N΄ × (10/8) × fOUT)/L) results in a line rate that is ≤12.5 Gbps. fOUT is the output sample rate and is
denoted by fS/DCM, where DCM = decimation ratio.
4 Can be controlled by the SPI.
AC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified
maximum sampling rate, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted.
Table 2.
Parameter1
ANALOG INPUT FULL SCALE
NOISE DENSITY2
SIGNAL-TO-NOISE RATIO (SNR)3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 737 MHz
fIN = 985 MHz
fIN = 1410 MHz
SNR AND DISTORTION RATIO (SINAD)3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 737 MHz
fIN = 985 MHz
fIN = 1410 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 737 MHz
fIN = 985 MHz
fIN = 1410 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 737 MHz
fIN = 985 MHz
fIN = 1410 MHz
Temp
Full
Full
AD9234-500
Min Typ Max
1.63
−150
AD9234-1000
Min Typ Max
1.34
−151
Unit
V p-p
dBFS/Hz
25°C 65.9
Full 65.1 65.8
25°C 65.6
25°C 65.3
25°C 64.2
25°C 63.6
25°C 62.2
64.2
61.6 63.9
63.4
63.1
61.6
60.7
58.8
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
25°C 65.8
Full 65.0 65.7
25°C 65.5
25°C 65.2
25°C 63.7
25°C 63.1
25°C 61.2
64.1
61.2 63.8
63.3
63.0
61.5
60.6
58.7
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
25°C 10.7
Full 10.5 10.6
25°C 10.6
25°C 10.5
25°C 10.3
25°C 10.2
25°C 9.9
10.4
9.9 10.3
10.2
10.2
9.9
9.8
9.5
Bits
Bits
Bits
Bits
Bits
Bits
Bits
25°C
Full
25°C
25°C
25°C
25°C
25°C
Rev. A | Page 6 of 66
77
84
85
85
87
75
75
71
89
70 80
79
80
81
79
78
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS

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