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| Número de pieza | STP1030 | |
| Descripción | High-Performance 64-Bit RISC Processor | |
| Fabricantes | SPARC | |
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SPARC Technology
Business
Preliminary
STP1030
May 1995
DATA SHEET
UltraSPARC-I
High-Performance 64-Bit RISC Processor
INTRODUCTION
The STP1030, UltraSPARC-I, is a high-performance, highly-integrated superscalar processor imple-
menting the SPARC V9 64-bit RISC architecture. The STP1030 is capable of sustaining the execution
of up to four instructions per cycle even in the presence of conditional branches and cache misses. This
sustained performance is supported by a decoupled Prefetch and Dispatch Unit with Instruction Buffer
to feed the Execution Unit. On the output side of the Execution Unit, Load and Store buffers com-
pletely decouple pipeline execution from data cache misses. Instructions predicted to be executed are
issued in program order to multiple functional units, execute in parallel and can complete out of order.
In order to further increase the number of instructions executed per cycle, instructions from different
blocks (e.g. instructions before and after a conditional branch) can be issued in the same group.
The STP1030 supports 2D, 3D graphics, image processing, video compression and decompression and
video effects through the sophisticated VISual Instruction Set. This instruction set supports high levels
of multimedia performance including real-time H.261 video compression/decompression and 2 streams
of MPEG-2 decompression at full broadcast quality with no additional hardware support.
Features:
• SPARC V9 Architecture Compliant
• Binary Compatible with all SPARC Application code
• VISual (Multimedia Capable) Instruction Set
• Multi-Processing Support
- Glueless 4-processor connection with minimum
latency
- Snooping or Directory Based Protocol Support
• 4-way SuperScalar Design with 9 execution units
- 4 Integer Execution Units
- 3 Floating-point Execution Units
- 2 Graphics Execution Units
• Selectable Little or Big Endian Byte Ordering
• 64-Bit Address Pointers
• 16KByte Non-blocking Data Cache
• 16KByte Instruction Cache
- In-Cache 2-bit Branch Prediction
- Single Cycle Branch Following
• Integrated 2nd Level Cache Controller
- Supports .5-4MBytes Cache Sizes
- Sustained throughput of 1 load/cycle
- 2.6Gbyte/sec Processor-Cache bandwidth
• Block Load/Store Instructions
- 1.3GByte/sec processor-memory bandwidth
- 600 MByte/sec Sustained Processor-Memory
Transfers
• Ease of Use
- JTAG Boundary scan
- Performance Instrumentation
• Technology/packaging
- 0.5um 4-layer metal CMOS process
- Operates at 3.3V
- 521 pin plastic Ball Grid Array (BGA)
• Power management
1 page  
High-Performance 64-Bit RISC Processor - UltraSPARC-I
Preliminary
STP1030
TABLE 1: Quick Pin Reference - System Interface
Symbol
SYSADR[35:0]
ADR_VLD
NODE_RQ[2:0]
SC_RQ
S_REPLY[[3:0]
DATA_STALL
P_REPLY[4:0]
NODEX_RQ
Type
I/O
I/O
I
I
I
I
O
O
Name and Function
Bidirectional UltraSPARC-I Bus transaction request bus. Maximum of 3 other masters and
1 system controller also connected to this bus.
Bidirectional radial UltraSPARC-I Bus signal between UltraSPARC-I and the System.
Driven by UltraSPARC-I to initiate SYSADR transactions to the System. Driven by System
to initiate Coherency, Interrupt or Slave transactions to UltraSPARC-I. Synchronous to sys-
tem clock.
UltraSPARC-I system address bus arbitration request from up to 3 other UltraSPARC-I Bus
ports that might be sharing the SYSADR. Used by UltraSPARC-I for the distributed
SYSADR arbitration protocol. Connection to other UltraSPARC-I Bus ports is strictly
dependent on the Master ID allocation. Synchronous to system clock.
UltraSPARC-I system address bus arbitration request from the system. Used by UltraS-
PARC-I for the distributed SYSADR arbitration protocol. Synchronous to system clock.
UltraSPARC-I system Reply packet, driven to UltraSPARC-I. Bit 4 of the UltraSPARC-I
Bus S_REPLY is not used by UltraSPARC-I. Synchronous to system clock.
This is asserted with or after an S_REPLY to hold output system data or signal the delay in
arrival of input data from the system.
UltraSPARC-I system reply packet, driven by UltraSPARC-I to the system. Synchronous
to system clock.
UltraSPARC-I system address bus arbitration request. Asserted when UltraSPARC-I needs
to drive SYSADR. Connected to all other UltraSPARC-I Bus ports which share this address
bus, and the system. Synchronous to system clock.
TABLE 2: Quick Pin Reference - External Cache Interface
Symbol
EDATA[127:0]
EDPAR[15:0]
TDATA[24:0]
TPAR[3:0]
Type
Name and Function
I/O Ecache Data bus. Connects UltraSPARC-I to the Ecache data rams and the UDB. Synchro-
nous to processor clock.
I/O Data bus parity. Odd parity is driven for all EDATA transfers, and checked if UltraSPARC-
I or the UDB is the receiver. The most significant bit serves as the parity for the most sig-
nificant byte of EDATA. Synchronous to processor clock.
I/O Bidirectional data bus for Ecache tag rams. Bits 24:22 carry the MOESI state: Dirty, Exclu-
sive, Valid. Bits[21:0] carry the physical address bits [40:19]. This allows a minimum cache
size of 512kbytes. All of the TDATA bits are used, even when the ecache is > 512kbytes.
This is because there is no sizing in the tag compare for ecache hit generation. Synchronous
to processor clock.
I/O Bidirectional data bus for Ecache tag rams. Odd Parity for TDATA[24:0]. TPAR[3] covers
TDATA[24:22]. TPAR[2] covers TDATA[21:16]. TPAR[1] covers TDATA{15:8],
TPAR[0] covers TDATA[7:0]. Synchronous to processor clock.
Sun Microsystems, Inc.
5
5 Page 
High-Performance 64-Bit RISC Processor - UltraSPARC-I
Preliminary
STP1030
Table 8 describes all transitions shown in Figure 4. It also shows the transactions that are initiated by
either UltraSPARC-I or the system and the acknowledgment that is expected following that transaction.
TABLE 8: Transitions Allowed for Cache Coherency Protocol
Transition
I→E
I→S
I→M
E→ M
E→S
E→I
S→M
S→I
Description
Transition
request to/by
UltraSPARC-I
Load miss; data coming from memory to an invalid P_RDS_REQ
line (no other cache has the data).
Load miss; data provided by another cache to an
invalid line.
Instruction cache miss, instructions provided either
from another cache or from memory.
P_RDS_REQ
P_RDSA_REQ
Store miss on an invalid line.
P_RDO_REQ
Store hit to an Exclusive Clean line in the cache.
No Transaction
Request from system to share this line (load miss from S_CPB_REQ
other processor).
i) A clean line is victimized by the processor.
P_RDS_REQ
ii) Request from system to invalidate this line (store or
miss from other processor to an Exclusive Clean line). P_RDSA_REQ
iii) Block Store with invalidate with also produce this or
transaction.
P_RDO_REQ
S_CPI_REQ
P_WRI_REQ
S_INV_REQ
Store hit to a Shared Clean line.
P_RDO_REQ
i) A Shared Clean line is victimized by UltraSPARC-I. P_RDS_REQ
ii) Another processor wants to write this shared datum. or
iii) Block Store with invalidate to a Shared Clean line, P_RDSA_REQ
either from this STP1030 or from another processor or
connected to the system.
P_RDO_REQ
S_INV_REQ
Acknowledgment
S_RBU
S_RBS
S_RBS
S_RBU
No Transaction
P_SACK | P_SACKD followed
by S_CRAB
S_RBU or S_RBS
S_RBS
S_RBU
P_SACK|P_SACKD followed
by
S_CRAB
S_WAB
P_SACK|P_SACKD
S_OAK
S_RBU or S_RBS
S_RBS
S_RBU
P_SACK|P_SACKD
P_WRI_REQ
S_INV_REQ
S_WAB
P_SACK|P_SACKD
M→0
Request from other processor to read a modified line, S_CPB_REQ
line stays modified (as opposed to M-->S).
P_SACK|P_SACKD
followed by S_CRAB
Sun Microsystems, Inc.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STP1030.PDF ] | |
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