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PDF NB3V60113G Data sheet ( Hoja de datos )
| Número de pieza | NB3V60113G | |
| Descripción | 1.8V Programmable OmniClock Generator | |
| Fabricantes | ON Semiconductor | |
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NB3V60113G
1.8 V Programmable
OmniClock Generator
with Single Ended (LVCMOS) and Differential
(LVDS/HCSL) Outputs
The NB3V60113G, which is a member of the OmniClock family, is
a one−time programmable (OTP), low power PLL−based clock
generator that supports any output frequency from 8 kHz to 200 MHz.
The device accepts fundamental mode parallel resonant crystal or a
single ended (LVCMOS) reference clock as input. It generates either
three single ended (LVCMOS) outputs, or one single ended output and
one differential (LVDS/HCSL) output. The output signals can be
modulated using the spread spectrum feature of the PLL
(programmable spread spectrum type, deviation and rate) for
applications demanding low electromagnetic interference (EMI).
Using the PLL bypass mode, it is possible to get a copy of the input
clock on any or all of the outputs. The device can be powered down
using the Power Down pin (PD#). It is possible to program the internal
input crystal load capacitance and the output drive current provided by
the device. The device also has automatic gain control (crystal power
limiting) circuitry which avoids the device overdriving the external
crystal.
www.onsemi.com
WDFN8
CASE 511AT
MARKING DIAGRAM
1
V0MG
G
V0 = Specific Device Code
M = Date Code
G = Pb−Free Device
(Note: Microdot may be in either location)
Features
• Member of the OmniClock Family of Programmable Clock
Generators
• Operating Power Supply: 1.8 V ± 0.1 V
• I/O Standards
♦ Inputs: LVCMOS, Fundamental Mode Crystal
♦ Outputs: LVCMOS
♦ Outputs: LVDS and HCSL
• 3 Programmable Single Ended (LVCMOS) Outputs
from 8 kHz to 200 MHz
• 1 Programmable Differential Clock Output up to
200 MHz
• Input Frequency Range
♦ Crystal: 3 MHz to 50 MHz
♦ Reference Clock: 3 MHz to 200 MHz
• Configurable Spread Spectrum Frequency Modulation
Parameters (Type, Deviation, Rate)
• Programmable Internal Crystal Load Capacitors
• Programmable Output Drive Current for Single Ended
Outputs
ORDERING INFORMATION
See detailed ordering and shipping information on page 19 of
this data sheet.
• Power Saving mode through Power Down Pin
• Programmable PLL Bypass Mode
• Programmable Output Inversion
• Programming and Evaluation Kit for Field
Programming and Quick Evaluation
• Temperature Range −40°C to 85°C
• Packaged in 8−Pin WDFN
• These are Pb−Free Devices
Typical Applications
• eBooks and Media Players
• Smart Wearables, Portable Medical and Industrial
Equipment
• Set Top Boxes, Printers, Digital Cameras and
Camcorders
© Semiconductor Components Industries, LLC, 2016
January, 2016 − Rev. 2
1
Publication Order Number:
NB3V60113G/D
1 page  
NB3V60113G
Programmable Clock Outputs
Output Type and Frequency
The NB3V60113G provides three independent single
ended LVCMOS outputs, or one single ended LVCMOS
output and one LVDS/HCSL differential output. The device
supports any single ended output or differential output
frequency from 8 kHz up to 200 MHz with or without
frequency modulation. It should be noted that certain
combinations of output frequencies and spread spectrum
configurations may not be recommended for optimal and
stable operation.
For differential clocking, CLK0 and CLK1 can be
configured as LVDS or HCSL. Refer to the Application
Schematic in Figure 4.
1.8 V
0.1 mF
0.01 mF
Crystal or
Reference
Clock Input
VDD
XIN / CLKIN
XOUT
PD#
NB3V60113G
VDD
CLK2
CLK1
CLK0
Single Ended Clock
Differential Clock
LVDS/HCSL
GND
Figure 4. Application Setup for Differential Output Configuration
Programmable Output Drive
The drive strength or output current of each of the
LVCMOS clock outputs is programmable. For VDD of 1.8 V
four distinct levels of LVCMOS output drive strengths can
be selected as mentioned in the DC Electrical
Characteristics. This feature provides further load drive and
signal conditioning as per the application requirement.
PLL BYPASS Mode
PLL Bypass mode can be used to buffer the input clock on
any of the outputs or all of the outputs. Any of the clock
outputs can be programmed to generate a copy of the input
clock.
Output Inversion
All output clocks of the NB3V60113G can be
phase inverted relative to each other. This feature can also be
used in conjunction with the PLL Bypass mode.
Spread Spectrum Frequency Modulation
Spread spectrum is a technique using frequency
modulation to achieve lower peak electromagnetic
interference (EMI). It is an elegant solution compared to
techniques of filtering and shielding. The NB3V60113G
modulates the output of its PLL in order to “spread” the
bandwidth of the synthesized clock, decreasing the peak
amplitude at the center frequency and at the frequency’s
harmonics. This results in significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most clock generators. Lowering EMI by
increasing a signal’s bandwidth is called ‘spread spectrum
modulation’.
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5
5 Page 
NB3V60113G
Table 9. AC ELECTRICAL CHARACTERISTICS
(VDD = 1.8 V ± 0.1 V, GND = 0 V, TA = −40°C to 85°C, Notes 15, 16 and 19)
Symbol
Parameter
Conditions
Min Typ Max Unit
DIFFERENTIAL OUTPUT (CLK1, CLK0) (VDD = 1.8 V ± 0.1 V; TA = −40°C to 85°C, Notes 15, 19 and 20)
tDC Output Clock Duty Cycle
VDD = 1.8 V;
Duty Cycle of Ref clock is 50%
%
PLL Clock 45 50 55
Reference Clock 40 50 60
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
15. Parameter guaranteed by design verification not tested in production.
16. Measurement taken from single ended clock terminated with test load capacitance of 5 pF and 15 pF and differential clock terminated
with test load of 2 pF. See Figures 6, 7 and 10.
17. Measurement taken from single−ended waveform
18. Measurement taken from differential waveform
19. AC performance parameters like jitter change based on the output frequency, spread selection, power supply and loading conditions of
the output. For application specific AC performance parameters, please contact ON Semiconductor.
20. Measured at fout = 100 MHz, No Frequency Modulation, fclkin = 25 MHz fundamental mode crystal and output termination as described
in Parameter Measurement Test Circuits
21. Period jitter Sampled with 10000 cycles, Cycle−cycle jitter sampled with 1000 cycles. Jitter measurement may vary. Actual jitter is
dependent on Input jitter and edge rate, number of active outputs, inputs and output frequencies, supply voltage, temperature, and output
load.
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11
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| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet NB3V60113G.PDF ] | |
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