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NB3H83905C の電気的特性と機能

NB3H83905CのメーカーはON Semiconductorです、この部品の機能は「1.8V/2.5V/3.3V Crystal Input to 1:6 LVTTL/LVCMOS Clock Fanout Buffer」です。


製品の詳細 ( Datasheet PDF )

部品番号 NB3H83905C
部品説明 1.8V/2.5V/3.3V Crystal Input to 1:6 LVTTL/LVCMOS Clock Fanout Buffer
メーカ ON Semiconductor
ロゴ ON Semiconductor ロゴ 




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NB3H83905C Datasheet, NB3H83905C PDF,ピン配置, 機能
NB3H83905C
1.8V/2.5V/3.3V Crystal Input
to 1:6 LVTTL/LVCMOS Clock
Fanout Buffer with OE
Description
The NB3H83905C is a 1.8 V, 2.5 V or 3.3 V VDD core Crystal input
to 1:6 LVTTL/LVCMOS fanout buffer with outputs powered by
flexible 1.8 V, 2.5 V, or 3.3 V supply VDDO (with VDD w VDDO). The
device accepts a fundamental Parallel Resonant crystal from 3 MHz to
40 MHz or a singleended LVCMOS Clock from up to 100 MHz.
Two synchronous LVTTL/LVCMOS Enable lines permit
independent control over outputs BCLK[0:4] and output BCLK5;
enabling or disabling only when the output is in LOW state
eliminating potential output glitching or runt pulse generation. When
unused, leave floating open, pins will default to HIGH state.
The 6 outputs drive 50 W series or parallel terminated transmission
lines. Parallel termination should be to 1/2 VCC. Series terminated
lines can drive 2 loads each, or 12 lines total.
Fit, Form, and Function compatible with ICS83905 and PI6C10806.
Features
Six Copies of LVTTL/LVCMOS Output Clock
Supply Operation VDD w VDDO:
1.8 V$0.2 V, 2.5 V $5% or 3.3 V $5% Core VDD
1.8 V$0.2 V, 2.5 V $5%, or 3.3 V $5% Output VDDO
Crystal Oscillator Interface
Crystal Input Frequency Range: 3 MHz to 40 MHz
Clock Input Frequency Range: Up to 100 MHz
LVCMOS compatible Enable Inputs
5 V Tolerant Enable Inputs
Low Output to Output Skew: 80 ps Max
Synchronous Output Enable
Phase Noise Floor 160 dBc (1 MHz)
Industrial Temperature Range
These are PbFree Devices
XTAL_IN/CLK
XTAL_OUT
C1
C2
ENABLE1
ENABLE2
SYNC
SYNC
BCLK0
BCLK1
BCLK2
BCLK3
BCLK4
BCLK5
Figure 1. Simplified Block Diagram
http://onsemi.com
MARKING
DIAGRAMS*
16
SOIC16
D SUFFIX
CASE 751B
NB3H83905G
ALYYWW
1
16
1
TSSOP16
DT SUFFIX
CASE 948F
16
NB3H
905C
ALYWG
G
1
1
QFN20
MN SUFFIX
CASE 485BH
20
1 NB3H
83905
ALYWG
G
A = Assembly Location
L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = PbFree Package
(*Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
November, 2012 Rev. 9
1
Publication Order Number:
NB3H83905C/D

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NB3H83905C pdf, ピン配列
NB3H83905C
Table 2. CLOCK ENABLE FUNCTION TABLE
Control Inputs
ENABLE1*
ENABLE2*
00
01
10
11
*Defaults HIGH when floating open.
BCLK0:BCLK4
LOW
LOW
Toggling
Toggling
Outputs
BCLK5
LOW
Toggling
LOW
Toggling
BCLK5
BCLK0:4
ENABLE2
ENABLE1
Figure 3. ENABLEx Control Timing Diagram
The ENABLEx control inputs will synchronously enable or disable the selected output(s). This control detects the falling
edge of the internal signal and asserts or deasserts the output after 3 clock cycles. When ENABLEx is LOW, the outputs are
disabled to a LOW state. When ENABLEx is HIGH, the outputs are enabled to toggle.
Table 3. RECOMMENDED CRYSTAL PARAMETERS
Crystal
Fundamental ATCut
Frequency
10 to 40 MHz
Load Capacitance*
1620 pF
Shunt Capacitance, C0
7 pF Max
Equivalent Series Resistance
50 W Max
Drive Level
1 mW
*See APPLICATION INFORMATION; Crystal Input Interface for CL loading
Table 4. ATTRIBUTES (Note 1)
Characteristics
ESD Protection
Human Body Model
Machine Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
> 2 kV
> 200 V
Level 1
UL94 code V0 A 1/8”
28 to 34
213 Devices
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NB3H83905C 電子部品, 半導体
NB3H83905C
Table 6. DC CHARACTERISTICS (continued)
Symbol
Characteristic
Min Typ Max Unit
VDD = 3.135 V to 3.465 V (3.3 V $5%); VDDO = 2.375 V to 2.625 V (2.5 V $5%); GND = 0 V, TA = 405C to +855C
IDD Core Quiescent Power Supply Current (ENABLEx = LOW)
10
mA
IDDO Output Quiescent Power Supply Current (ENABLEx = LOW)
4 mA
VIH Input HIGH Voltage ENABLEx, XTAL_IN/CLK
2
VDD +
V
0.3 V
VIL Input LOW Voltage ENABLEx, XTAL_IN/CLK
VOH Output HIGH Voltage (IOH = 1 mA)
Output HIGH Voltage (Note 4)
0.3 0.8 V
2.0 V
1.8
VOL Output LOW Voltage (IOL = 1 mA)
Output LOW Voltage (Note 4)
0.4 V
0.45
CIN Input Capacitance
4
CPD Power Dissipation Capacitance (per Output) (Note 4)
18
ROUT Output Impedance (Note 4)
7
VDD = 3.135 V to 3.465 V (3.3 V $5%); VDDO = 1.6 V to 2.0 V (1.8 V $0.2 V.); GND = 0 V, TA = 405C to +855C
IDD Core Quiescent Power Supply Current (ENABLEx = LOW)
10
pF
pF
W
mA
IDDO Output Quiescent Power Supply Current (ENABLEx = LOW)
3 mA
VIH Input HIGH Voltage ENABLEx, XTAL_IN/CLK
2
VDD +
V
0.3 V
VIL Input LOW Voltage ENABLEx, XTAL_IN/CLK
0.3
VOH Output HIGH Voltage (Note 4)
VDDO0.3
VOL Output LOW Voltage (Note 4)
CIN Input Capacitance
4
CPD Power Dissipation Capacitance (per Output) (Note 4)
16
ROUT Output Impedance (Note 4)
10
VDD = 2.375 V to 2.625 V (2.5 V $5%); VDDO = 1.6 V to 2.0 V (1.8 V $0.2 V); GND = 0 V, TA= 405C to +855C
IDD Core Quiescent Power Supply Current (ENABLEx = LOW)
0.8
0.35
8
V
V
V
pF
pF
W
mA
IDDO Output Quiescent Power Supply Current (ENABLEx = LOW)
3 mA
VIH Input HIGH Voltage ENABLEx, XTAL_IN/CLK
1.7
VDD +
V
0.3 V
VIL Input LOW Voltage ENABLEx, XTAL_IN/CLK
0.3 0.7 V
VOH Output HIGH Voltage (Note 4)
VDDO0.3
V
VOL Output LOW Voltage (Note 4)
0.35 V
CIN Input Capacitance
4 pF
CPD Power Dissipation Capacitance (per Output) (Note 4)
16 pF
ROUT Output Impedance (Note 4)
10 W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
4. Parallel terminated 50 W to VDDO/2 (see Figure 5).
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部品番号部品説明メーカ
NB3H83905C

1.8V/2.5V/3.3V Crystal Input to 1:6 LVTTL/LVCMOS Clock Fanout Buffer

ON Semiconductor
ON Semiconductor


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