DataSheet.jp

NB3H5150-01 の電気的特性と機能

NB3H5150-01のメーカーはON Semiconductorです、この部品の機能は「2.5V / 3.3V Low Noise Multi-Rate Clock Generator」です。


製品の詳細 ( Datasheet PDF )

部品番号 NB3H5150-01
部品説明 2.5V / 3.3V Low Noise Multi-Rate Clock Generator
メーカ ON Semiconductor
ロゴ ON Semiconductor ロゴ 




このページの下部にプレビューとNB3H5150-01ダウンロード(pdfファイル)リンクがあります。

Total 19 pages

No Preview Available !

NB3H5150-01 Datasheet, NB3H5150-01 PDF,ピン配置, 機能
NB3H5150-01
2.5V / 3.3V Low Noise
Multi-Rate Clock Generator
Description
The NB3H5150−01 is a high performance Multi−Rate Clock
generator which simultaneously synthesizes up to four different
frequencies from a single PLL using a 25 MHz input reference. The
www.onsemi.com
reference frequency can be provided by a crystal, LVCMOS/LVTTL,
LVPECL, HCSL or LVDS differential signals. The REFMODE pin
will select the reference source.
MARKING
DIAGRAM*
Three output banks (CLK1A/CLK1B to CLK3A/CLK3B) produce
user selectable frequencies of: 33.33 MHz, 50 MHz, 100 MHz,
125 MHz, or 156.25 MHz and have ultra−low noise/jitter performance
of less than 0.3 ps.
The fourth output bank (CLK4A/CLK4B) can produce the
1 32
1
QFN32
MN SUFFIX
CASE 485CE
NB3H
5150−01
AWLYYWWG
following integer and FRAC−N frequencies in pin−strap mode:
25 MHz, 33.33 MHz, 66.66 MHz, 100 MHz, 125 MHz, 133.33 MHz,
156.25 MHz or 161.1328 MHz.
Each output block can create two single−ended in−phase LVCMOS
outputs or one differential pair of LVPECL outputs.
Each of the four output blocks is independently powered by a
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
separate VDDO, 2.5 V/3.3 V for LVPECL, 1.8 V/2.5 V/3.3 V for
LVCMOS.
The serial (I2C and SMBUS) interface can be used to load register
*For additional marking information, refer to
Application Note AND8002/D.
files into the NB3H5150−01 to program a variety of functions
including the frequencies and output levels of each output which can
ORDERING INFORMATION
be individually enabled and disabled.
See detailed ordering and shipping information on page 18 of
this data sheet.
Features
Flexible Input Reference − 25 MHz Crystal, Oscillator,
1 ps maximum RMS Phase Jitter FRAC−N (CLK4)
Single−Ended or Differential Clock
161.1328 MHz
Four Independent User−Programmable Clock
I2C / SMBus Compatible Interface
Frequencies from 25 MHz to 250 MHz
Independently Configurable Outputs:
Up to Eight LVCMOS Single Ended outputs or,
Up to Four Differential LVPECL Outputs or any
combination of LVCMOS and LVPECL
Flexible Input/Core and Output Power Supply
Combinations:
VDD (Core) = 3.3 V ±5% or 2.5 V ±5%
VDDOn (Outputs) = 3.3 V ±5% or 2.5 V ±5% or
1.8 V ±5% (LVCMOS Only)
Independent Power Supply for each Output Bank
300 ps max Output Rise and Fall Times, LVPECL
1000 ps max Output Rise and Fall Times, LVCMOS
300 fs maximum RMS Phase Jitter Interger−N
(CLK1:4) 156.25 MHz
−40°C to +85°C Ambient Operating Temperature
Zero ppm Multiplication Error
Fractional Divide Ratios for Implementing Arbitrary
FEC/Inverse−FEC Ratios
For Additional Pin−strap Frequency and Output Type
Combinations, Contact ON Semiconductor Sales Office
32−Pin QFN, 5 mm x 5 mm
This is a Pb−Free Device
Applications
Telecom
Networking
Ethernet
SONET
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 1
1
Publication Order Number:
NB3H5150−01/D

1 Page





NB3H5150-01 pdf, ピン配列
NB3H5150−01
Table 1. PIN DESCRIPTION
Pin Name
I/O
1 CLK_XTAL2
Crystal or
LVPECL/LVDS
Input
2 REFMODE LVTTL/LVCMOS
Input
3 SDA LVTTL/LVCMOS
Input
4 SCL/PD LVTTL/LVCMOS
Input
5 VDD
6 FS1
7 FS2
8 FS3
9 FS4A
10 FS4B
11 LDO4
12 AVDD3
13 LDO3
14 CLK4A
Power
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
LVTTL/LVCMOS
Input
Power
Power
Power
Output
15 CLK4B
16 VDDO4
17 MMC
Output
Power
LVTTL/LVCMOS
Input
18 CLK3B
19 CLK3A
Output
Output
20 VDDO3
21 VDDO2
22 CLK2A
Power
Power
Output
23 CLK2B
24 FTM
25 VDDO1
26 CLK1B
27 CLK1A
Output
Power
Output
Output
28 AVDD2
29 LDO2
30 AVDD1
31 LDO1
Power
Power
Power
Power
Description
Crystal Output or Differential Clock Input (complementary); If CLK_XTAL1 is used as
single−ended input, CLK_XTAL2 must be connected to ground. See Table 2.
Reference Input Select to either use a crystal, or overdrive with a single−ended or
differential input; see Table 2. Internal pull−down.
Serial Data Input for I2C/SMBus compatible; Defaults High when left open; internal pull−up.
5V tolerant.
Serial Clock Input for I2C/SMBus compatible; Defaults High when left open; internal
pull−up.
SCL/PD is also a device power−down pin (when High) in pin−strap mode only. 5V tolerant.
3.3 V / 2.5 V Positive Supply Voltage for the Inputs and Core
Frequency Select 1 for DIV1, CLK1A & CLK1B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 3.
Frequency Select 2 for DIV2, CLK2A & CLK2B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 3.
Frequency Select 3 for DIV3, CLK3A, & CLK3B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 3.
Frequency Select 4A for DIV4, CLK4A & CLK4B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 4.
Frequency Select 4B for DIV4, CLK4A & CLK4B; Three–level input buffer; Default is
mid−logic level; internal RPull−up and RPull−down. See Table 4.
1.8 V LDO − Install Power Conditioning Bypass Capacitor to Ground
3.3 V / 2.5 V Positive Supply Voltage for Analog circuits. AVDD3 = VDD.
1.8V LDO − Install Power Conditioning Bypass Capacitor to Ground
LVCMOS (single−ended) or Non− Inverted Differential LVPECL Clock A for Channel 4
Output
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 4 Output
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK4A/4B Outputs
Mix Mode Control Pin for use as a combination of FSn settings and I2C setting for the
CLK(n) outputs in the I2C mode; see Table 6. No logic level default; use a RPull−up resistor
for High or a RPull−down resistor for Low.
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 3 Output
LVCMOS (single−ended) or Non−Inverted Differential LVPECL Clock A for Channel 3
Output
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK3A/3B Outputs
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK2A/2B Outputs
LVCMOS (single−ended) or Non− Inverted Differential LVPECL Clock A for Channel 2
Output
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 2 Output
Factory Test Mode. Must connect this pin to Ground.
3.3 V / 2.5 V / 1.8 V Positive Supply Voltage for the CLK1A/1B Outputs
LVCMOS (single−ended) or Inverted Differential LVPECL Clock B for Channel 1 Output
LVCMOS (single−ended) or Non−Inverted Differential LVPECL Clock A for Channel 1
Output
3.3 V / 2.5 V Positive Supply Voltage for Analog circuits. AVDD2 = VDD.
1.8 V LDO − Install Power Conditioning Bypass Capacitor to Ground
3.3 V / 2.5 V Positive Supply Voltage for Analog circuits. AVDD1 = VDD.
1.8 V LDO − Install Power Conditioning Bypass Capacitor to Ground
www.onsemi.com
3


3Pages


NB3H5150-01 電子部品, 半導体
NB3H5150−01
become effective and will begin to output the
selected frequencies.
2. Subsequent changes to any FS pin(s) will cause
the associated CLK(n) output(s) to momentarily
go to static levels, and then to resume at the new
frequency; CLK(n) will follow the FS(n) pin
programmable Tables 3 and 4 for output
frequencies and interface levels.
Note that in changing from LVPECL to LVCMOS
(or vice−versa), output logic levels cannot be
guaranteed. This is because the receiver inputs are
not likely to change in a given application, and the
LVPECL output loading in the application will
also not change. It is logical to presume that the
output type will be predetermined and fixed.
Therefore, in a system/application, the user should
be aware that subsequent change to the FS pin
should only change frequency, and not output type.
3. Power off/on cycle will repeat the entire sequence
4. Power Down
To initiate the Power−Down mode, the SDA pin
must be LOW and remain LOW. If the SCL/PD
pin is taken HIGH at any time, the device enters a
complete power−down mode with a current
consumption of less than 1 mA for the entire
device. When SCL/PD is subsequently taken
LOW, the device will function as though power
were removed and re−applied. That is, sequencing
will begin at #1.
Power−down is also available via I2C with a
register file.
FS(n) Pin Programmable Selection of Output Frequencies and Levels
Table 3. NB3H5150−01MNTXG − CLK1A:3A & CLK1B:3B OUTPUT FREQUENCY
SELECT TABLE WITH 25 MHz CRYSTAL
Logic Level
Low
FS1 (CLK1)
(MHz)
156.25 (LVPECL)
FS2 (CLK2)
(MHz)
156.25 (LVPECL)
FS3 (CLK3)
(MHz)
156.25 (LVPECL)
Mid / Float*
25.00 (LVPECL)
100.00 (LVPECL)
125.00 (LVPECL)
High
50.00 (LVPECL)
125.00 (LVPECL)
50.00 (LVPECL)
*(Default)
Table 4. NB3H5150−01MNTXG − CLK4A & CLK4B OUTPUT FREQUENCY
SELECT TRUTH TABLE (MHz) WITH 25 MHz CRYSTAL*
FS4A
FS4B
CLK4 (MHz)
Divider Type
Low Low 33.33 (LVCMOS)
Integer
Low
Mid / Float
66.66 (LVCMOS)
Fractional
Low
High
133.33 (LVCMOS)
Fractional
Mid / Float
Low
133.33 (LVPECL)
Fractional
Mid / Float*
Mid / Float*
156.25 (LVPECL)
Integer
Mid / Float
High
125.00 (LVPECL)
Integer
High Low 25.00 (LVPECL)
Integer
High
Mid / Float
100.00 (LVPECL)
Integer
High
High
161.1328 (LVPECL)
Fractional
*(Default)
www.onsemi.com
6

6 Page



ページ 合計 : 19 ページ
 
PDF
ダウンロード
[ NB3H5150-01 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
NB3H5150-01

2.5V / 3.3V Low Noise Multi-Rate Clock Generator

ON Semiconductor
ON Semiconductor


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap