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IS43LR32800F の電気的特性と機能

IS43LR32800FのメーカーはISSIです、この部品の機能は「2M x 32Bits x 4Banks Mobile DDR SDRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS43LR32800F
部品説明 2M x 32Bits x 4Banks Mobile DDR SDRAM
メーカ ISSI
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IS43LR32800F Datasheet, IS43LR32800F PDF,ピン配置, 機能
IS43/46LR32800F
2M x 32Bits x 4Banks Mobile DDR SDRAM
Description
The IS43/46LR32800F is 268,435,456 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 2,097,152 words x
32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted
on a 32-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock.
The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are
compatible with LVCMOS.
Features
• JEDEC standard 1.8V power supply.
VDD = 1.8V, VDDQ = 1.8V
Four internal banks for concurrent operation
• MRS cycle with address key programs
- CAS latency 2, 3 (clock)
- Burst length (2, 4, 8, 16)
- Burst type (sequential & interleave)
• Fully differential clock inputs (CK, /CK)
• All inputs except data & DM are sampled at the rising
edge of the system clock
• Data I/O transaction on both edges of data strobe
• Bidirectional data strobe per byte of data (DQS)
DM for write masking only
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
64ms refresh period (4K cycle)
• Auto & self refresh
Concurrent Auto Precharge
Maximum clock frequency up to 200MHZ
Maximum data rate up to 400Mbps/pin
Power Saving support
- PASR (Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Deep Power Down Mode
- Programmable Driver Strength Control by Full Strength,
or 3/4, 1/2, 1/4, 1/8 of Full Strength
• Status Register Read (SRR)
• LVCMOS compatible inputs/outputs
Packages:
- 90-Ball FBGA
- 152-Ball PoP BGA
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Rev. A | February 2013
www.issi.com - [email protected]
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IS43LR32800F pdf, ピン配列
Figure2: 152-Ball VFBGA Ball Assignment
IS43/46LR32800F
[Top View]
Notes:
1. Although not bonded to the die, these pins may be connected on the package substrate.
2. A12 is No Connect (NC) for 256Mb (8Mx32). Reserve for future use, as A12 (R21) is used for 1Gb (32Mx32) and
512Mb (16Mx32).
Rev. A | February 2013
www.issi.com - [email protected]
3


3Pages


IS43LR32800F 電子部品, 半導体
IS43/46LR32800F
Figure4 : Simplified State Diagram
Power
Applied
Power
On
DPDSX
Deep Power
Down
Precharge
All Banks
DPDS
Self
Refresh
REFS
REFSX
MRS
SRR
Read
MRS
EMRS
MRS
Active
Power
Down
CKEH
Idle
All Banks
Precharged
CKEL
REFA
CKEH
ACT
Precharge
Power
Down
Auto
Refresh
CKEL
Row
Active
Burst
Stop
WRITE
WRITE
WRITE
WRITE A READ A
READ
READ
BST
READ
READ
WRITE A
WRITE A
PRE
PRE
PRE
PRE
Precharge
PREALL
READ A
READ A
Automatic
sequence
Rev. A | February 2013
ACT = Active
BST = Burst
CKEL = Enter Power- Down
CKEH = Exit Power-Down
DPDS = Enter Deep Power-Down
DPDSX = Exit Deep Power- Down
EMRS = Ext. Mode Reg. Set
MRS = Mode Register Set
PRE = Precharge
PREALL= Precharge All Banks
REFA = Auto Refresh
REFS = Enter Self Refresh
REFSX = Exit Self Refresh
READ = Read w/o Auto Precharge
READ A = Read with Auto Precharge
SRR = Status Register Read
WRITE = Write w/o Auto Precharge
WRITE A = Write with Auto Precharge
www.issi.com - [email protected]
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共有リンク

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部品番号部品説明メーカ
IS43LR32800F

2M x 32Bits x 4Banks Mobile DDR SDRAM

ISSI
ISSI
IS43LR32800G

2M x 32Bits x 4Banks Mobile DDR SDRAM

ISSI
ISSI


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