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IS43LR16160G の電気的特性と機能

IS43LR16160GのメーカーはISSIです、この部品の機能は「4M x 16Bits x 4Banks Mobile DDR SDRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS43LR16160G
部品説明 4M x 16Bits x 4Banks Mobile DDR SDRAM
メーカ ISSI
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IS43LR16160G Datasheet, IS43LR16160G PDF,ピン配置, 機能
IS43/46LR16160G
4M x 16Bits x 4Banks Mobile DDR SDRAM
Description
The IS43/46LR16160G is 268,435,456 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 4,194,304 words x
16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted
on a 16-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock.
The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are
compatible with LVCMOS.
Features
• JEDEC standard 1.8V power supply
• VDD = 1.8V, VDDQ = 1.8V
Four internal banks for concurrent operation
• MRS cycle with address key programs
- CAS latency 2, 3 (clock)
- Burst length (2, 4, 8, 16)
- Burst type (sequential & interleave)
• Fully differential clock inputs (CK, /CK)
• All inputs except data & DM are sampled at the rising
edge of the system clock
• Data I/O transaction on both edges of data strobe
• Bidirectional data strobe per byte of data (DQS)
DM for write masking only
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
64ms refresh period (8K cycle)
• Auto & self refresh
Concurrent Auto Precharge
Maximum clock frequency up to 200MHZ
Maximum data rate up to 400Mbps/pin
• Power Saving support
- PASR (Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Deep Power Down Mode
- Programmable Driver Strength Control by Full Strength
or 3/4, 1/2, 1/4, or 1/8 of Full Strength
• Status Register Read (SRR)
• LVCMOS compatible inputs/outputs
• 60-Ball FBGA package
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Rev. A | November 2013
www.issi.com - [email protected]
1

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IS43LR16160G pdf, ピン配列
IS43/46LR16160G
Table2 : Pin Descriptions
Symbol
Type
CK, /CK
Input
CKE Input
/CS Input
BA0, BA1
Input
A0~A12
/RAS, /CAS, /WE
LDM, UDM
Input
Input
Input
Function
System Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input Mask
Descriptions
The system clock input. CK and /CK are differential clock
inputs. All address and control input signals are registered on
the crossing of the rising edge of CK and falling edge of /CK.
Input and output data is referenced to the crossing of CK and
/CK.
CKE is clock enable controls input. CKE HIGH activates, and
CKE LOW deactivates internal clock signals, and device input
buffers and output drivers. CKE is synchronous for all functions
except for SELF REFRESH EXIT, which is achieved
asynchronously.
/CS enables (registered Low) and disables (registered High)
the command decoder. All commands are masked when /CS
IS REGISTERED high. /CS provides for external bank selection
on systems with multiple banks. /CS is considered part of the
command code.
BA0 and BA1 define to which bank an ACTIVE, READ, WRITE,
or PRECHARGE command is being applied. BA0 and BA1 also
determine which mode register (standard mode register or
extended mode register) is loaded during a LOAD MODE
REGISTER command.
Row Address
Column Address
Auto Precharge
: RA0~RA12
: CA0~CA8
: A10
/RAS, /CAS and /WE define the operation.
Refer function truth table for details.
DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM balls are input-only.
DQ0~DQ15
In/Output
Data Input/Output
Data input/output pin.
LDQS, UDQS
VDD
VSS
VDDQ
VSSQ
NC
In/Output
Supply
Supply
Supply
Supply
NC
Data Input/Output
Strobe
Power Supply
Ground
DQ Power Supply
DQ Ground
No Connection
Output with read data, input with write data. DQS is edge-
aligned with read data, centered in write data. Data strobe is
used to capture data.
Power supply
Ground
Power supply for DQ
Ground for DQ
No connection.
Rev. A | November 2013
www.issi.com - [email protected]
3


3Pages


IS43LR16160G 電子部品, 半導体
IS43/46LR16160G
Figure4 : Mode Register Set (MRS) Definition
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mode Register (Mx)
00000000
CAS Latency BT Burst Length
M6 M5 M4 CAS Latency
000
Reserved
001
Reserved
010
2
011
3
100
Reserved
101
Reserved
110
Reserved
111
Reserved
Note:
M14(BA1) = 0 and M13(BA0) = 0 to select Mode Register
M3 Burst Type
0 Sequential
1 Interleave
M2 M1 M0
Burst Length
M3 = 0
M3 = 1
0 0 0 Reserved Reserved
001
2
2
010
4
4
011
8
8
100
16
16
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Reserved Reserved
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is
selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
address, as shown in Table 3.
Rev. A | November 2013
www.issi.com - [email protected]
6

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部品番号部品説明メーカ
IS43LR16160F

4M x 16Bits x 4Banks Mobile DDR SDRAM

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IS43LR16160G

4M x 16Bits x 4Banks Mobile DDR SDRAM

ISSI
ISSI


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