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IS46LD16640A の電気的特性と機能

IS46LD16640AのメーカーはISSIです、この部品の機能は「1Gb Mobile LPDDR2 S4 SDRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS46LD16640A
部品説明 1Gb Mobile LPDDR2 S4 SDRAM
メーカ ISSI
ロゴ ISSI ロゴ 




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IS46LD16640A Datasheet, IS46LD16640A PDF,ピン配置, 機能
IS43/46LD16640A
IS43/46LD32320A
1Gb (x16, x32) Mobile LPDDR2 S4 SDRAM
AUGUST 2014
FEATURES
Low-voltage Core and I/O Power Supplies
VDD2 = 1.14-1.30V, VDDCA/VDDQ = 1.14-1.30V,
VDD1 = 1.70-1.95V
High Speed Un-terminated Logic(HSUL_12) I/O
Interface
Clock Frequency Range : 10MHz to 400MHz
(data rate range : 20Mbps to 800 Mbps per I/O)
Four-bit Pre-fetch DDR Architecture
Multiplexed, double data rate, command/ad-
dress inputs
Eight internal banks for concurrent operation
Bidirectional/differential data strobe per byte of
data (DQS/DQS#)
Programmable Read/Write latencies(RL/WL)
and burst lengths(4,8 or 16)
Per-bank refresh for concurrent operation
ZQ Calibration
On-chip temperature sensor to control self re-
fresh rate
Partial –array self refresh(PASR) – Bank & Seg-
ment masking
Deep power-down mode(DPD)
Operation Temperature
Commercial (TC = 0°C to 85°C)
Industrial (TC = -40°C to 85°C)
Automotive, A1 (TC = -40°C to 85°C)
Automotive, A2 (TC = -40°C to 105°C)
OPTIONS
Configuration:
− 64Mx16 (8M x 16 x 8 banks)
− 32Mx32 (4M x 32 x 8 banks)
Package:
− 134-ball BGA for x16 / x32
− 168-ball PoP BGA for x32
description
The IS43/46LD16640A/32320A is 1,073,741,824 bits
CMOS Mobile Double Data Rate Synchronous DRAMs
organized as 8 banks (S4). The deviceis organized as 8
banks of 8Meg words of 16bits or 4Meg words of 32bits.
This product uses a double-data-rate architecture to
achieve high-speed operation. The double data rate
architecture is essentially a 4N prefetch architecture
with an interface designed to transfer two data words
per clock cycle at the I/O pins. This product offers fully
synchronous operations referenced to both rising and
falling edges of the clock. The data paths are internally
pipelined and 4n bits prefetched to achieve very high
bandwidth.
ADDRESS TABLE
Parameter
Row Addresses
Column Addresses
Bank Addresses
Refresh Count
32Mx32
R0-R12
C0-C8
BA0-BA2
4K
64Mx16
R0-R12
C0-C9
BA0-BA2
4K
kEY TIMING PARAMETERS
Speed
Grade
-25
-3
Data
Rate
(Mb/s)
800
667
Write Read tRCD/
Latency Latency tRP
3 6 Typical
2 5 Typical
Note: Other clock frequencies/data rates supported; please
refer to AC timing tables.
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. A
8/6/2014

1 Page





IS46LD16640A pdf, ピン配列
IS43/46LD16640A
IS43/46LD32320A
BALL ASSIGNMENTS AND DESCRIPTIONS
134-ball FBGA (x16), 0.65mm pitch
1 2 3 4 5 6 7 8 9 10
A DNU
DNU
DNU DNU A
B DNU
NC
NC
VDD2 VDD1
NC
NC
NC DNU B
C VDD1
VSS
RFU
VSS VSSQ VDDQ NC VSSQ VDDQ C
D VSS
VDD2
ZQ
VDDQ
NC
NC
NC
NC VSSQ D
E VSSCA
CA9
CA8
NC NC NC DQ15 VDDQ VSSQ E
F VDDCA CA6
CA7
VSSQ
DQ11
DQ13
DQ14
DQ12
VDDQ F
G VDD2
CA5 Vref(CA)
DQS1_c DQS1_t DQ10
DQ9
DQ8 VSSQ G
H VDDCA VSS
CK_c
DM1 VDDQ
H
J VSSCA
NC
CK_t
VSSQ VDDQ VDD2
VSS Vref(DQ)
J
K CKE RFU RFU
DM0 VDDQ
K
L CS_n RFU RFU
DQS0_c DQS0_t DQ5 DQ6 DQ7 VSSQ L
M CA4 CA3 CA2
VSSQ DQ4 DQ2 DQ1 DQ3 VDDQ M
N VSSCA VDDCA CA1
NC NC NC DQ0 VDDQ VSSQ N
P VSS VDD2 CA0
VDDQ
NC
NC
NC
NC VSSQ P
R VDD1
VSS
NC
VSS VSSQ VDDQ NC VSSQ VDDQ R
T DNU
U DNU
NC
DNU
NC
VDD2 VDD1
NC
NC NC DNU T
DNU DNU U
1 2 3 4 5 6 7 8 9 10
DQ
CA
Power
Ground
No ball
ZQ
Clock
NC, DNU, RFU
Top View (ball down)
Integrated Silicon Solution, Inc. — www.issi.com 3
Rev. A
8/6/2014


3Pages


IS46LD16640A 電子部品, 半導体
IS43/46LD16640A
IS43/46LD32320A
Name
VDD1
VDD2
VDDCA
VDDQ
VREF(CA)
VREF(DQ)
VSS
VSSCA
VSSQ
ZQ
Type Description
Supply Core Power Supply 1
Supply Core Power Supply 2
Supply Input Receiver Power Supply: Power supply for CA0-9, CKE, CS_n, CK_t, and CK_c
input buffers.
Supply I/O Power Supply: Power supply for Data input/output buffers.
Supply Reference Voltage for CA Command and Control Input Receiver: Reference voltage
for all CA0-9, CKE, CS_n, CK_t, and CK_c input buffers.
Supply Reference Voltage for DQ Input Receiver: Reference voltage for all Data input buffers.
Supply Ground
Supply Ground for Input Receivers
Supply I/O Ground
I/O Reference Pin for Output Drive Strength Calibration
NOTE 1 Data includes DQ and DM.
6 Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
8/6/2014

6 Page



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部品番号部品説明メーカ
IS46LD16640A

1Gb Mobile LPDDR2 S4 SDRAM

ISSI
ISSI


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