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PDF CY62157DV30 Data sheet ( Hoja de datos )
| Número de pieza | CY62157DV30 | |
| Descripción | 8-Mbit (512K x 16) MoBL Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62157DV30 MoBL®
8-Mbit (512K x 16) MoBL Static RAM
Features
■ Temperature ranges
❐ Industrial: –40 °C to 85 °C
■ Very high speed: 55 ns
■ Wide voltage range: 2.20 V–3.60 V
■ Pin-compatible with CY62157CV25, CY62157CV30, and
CY62157CV33
■ Ultra-low active power
❐ Typical active current: 1.5 mA @ f = 1 MHz
❐ Typical active current: 12 mA @ f = fmax
■ Ultra-low standby power
■ Easy memory expansion with CE1, CE2, and OE features
■ Automatic power-down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
■ Available in Pb-free and non Pb-free 48-ball fine ball grid
array (FBGA), and Pb-free 44-pin thin small outline package
(TSOPII) package
Functional Description
The CY62157DV30 is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
Logic Block Diagram
A10
A9
AAA876
A5
A4
A3
A2
AA01
DATA-IN DRIVERS
512K × 16
RAM Array
COLUMN DECODER
Power-down
Circuit
This is ideal for providing More Battery Life (MoBL®) in
portable applications such as cellular telephones.The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can also be put into
standby mode when deselected (CE1 HIGH or CE2 LOW or
both BHE and BLE are HIGH). The input/output pins (I/O0
through I/O15) are placed in a high-impedance state when:
deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or during a write operation (CE1
LOW, CE2 HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enables
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0
through I/O7), is written into the location specified on the
address pins (A0 through A18). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A18).
Reading from the device is accomplished by taking Chip
Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O8 to I/O15. See the truth table for a complete description
of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
I/O0–I/O7
I/O8–I/O15
BHE
WE
OE
BLE
CE2
CE1
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05392 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 25, 2010
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CY62157DV30 MoBL®
Thermal Resistance
Parameter[11]
Description
JA Thermal resistance
(Junction to ambient)
JC Thermal resistance
(Junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch, four-layer
printed circuit board
AC Test Loads and Waveforms
FBGA
39.3
9.69
TSOP II
35.62
9.13
Unit
C / W
C / W
VCC
OUTPUT
R1
30 pF / 50 pF
INCLUDING
JIG AND
SCOPE
VCC
GND
10%
ALL INPUT PULSES
90%
90%
10%
R2
Rise Time = 1 V/ns
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
RTH
V
Parameters
2.50 V
3.0 V
R1
16667
1103
R2
15385
1554
RTH
8000
645
VTH 1.20 1.75
Data Retention Characteristics (Over the Operating Range)
Unit
V
Parameter
VDR
ICCDR
tCDR[11]
tR[13]
Description
VCC for data retention
Data retention current
Chip deselect to data
retention time
Operation recovery time
Conditions
VCC= 1.5 V
CE1 > VCC – 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
Ind’l
Min Typ[12] Max
1.5 –
–
––4
0–
55 –
–
–
Data Retention Waveform[14]
VCC
CBHEE1 .oBrLE
or
CE2
VCC, min.
tCDR
DATA RETENTION MODE
VDR > 1.5 V
VCC, min.
tR
Unit
V
A
ns
ns
Notes
11. Tested initially and after any design or process changes that may affect these parameters
12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C
13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s.
14. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05392 Rev. *J
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CY62157DV30 MoBL®
Ordering Information
Speed
(ns)
55
Ordering Code
CY62157DV30LL-55BVI
CY62157DV30LL-55BVXI
CY62157DV30LL-55ZSXI
Ordering Code Definition
Package
Diagram
51-85150
51-85087
Package Type
48-ball (6 x 8 x 1 mm) FBGA
48-ball (6 x 8 x 1 mm) FBGA (Pb-free)
44-pin TSOP II (Pb-free)
CY 621 5 7D V30 LL 55 XXX X
Temperature Grade
I = Industrial
Package Type :
ZSX : TSOP II (Pb-free)
BVX : VFBGA (Pb-free)
BV : VFBGA
Speed Grade
Low Power
Voltage = 3.0
Bus W idth = X16
D = 130nm Technology
Density = 8Mbit
MoBL SRAM Family
Company ID: CY = Cypress
Operating
Range
Industrial
Document #: 38-05392 Rev. *J
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