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Número de pieza MCF5272
Descripción Microprocessor
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No Preview Available ! MCF5272 Hoja de datos, Descripción, Manual

MCF5272 ColdFire® Integrated
Microprocessor
User’s Manual
ColdFire®
Microcontrollers
MCF5272UM
Rev. 3
03/2007
freescale.com

1 page




MCF5272 pdf
List of Figures
Figure
Number
Title
Page
Number
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
3-1
3-2
4-1
4-2
4-3
4-4
4-5
5-1
5-2
5-3
5-4
5-5
5-6
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5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
MCF5272 Block Diagram ........................................................................................................ 1-2
ColdFire Pipeline..................................................................................................................... 2-2
ColdFire Multiply-Accumulate Functionality Diagram.............................................................. 2-3
ColdFire Programming Model ................................................................................................. 2-5
Condition Code Register (CCR).............................................................................................. 2-6
Status Register (SR) ............................................................................................................... 2-8
Vector Base Register (VBR) ................................................................................................... 2-8
Organization of Integer Data Formats in Data Registers ...................................................... 2-10
Organization of Integer Data Formats in Address Registers................................................. 2-10
Memory Operand Addressing ............................................................................................... 2-11
Exception Stack Frame Form................................................................................................ 2-27
ColdFire MAC Multiplication and Accumulation ...................................................................... 3-1
MAC Programming Model....................................................................................................... 3-2
SRAM Base Address Register (RAMBAR) ............................................................................. 4-3
ROM Base Address Register (ROMBAR).............................................................................. 4-5
Instruction Cache Block Diagram............................................................................................ 4-8
Cache Control Register (CACR) ........................................................................................... 4-12
Access Control Register Format (ACRn) .............................................................................. 4-14
Processor/Debug Module Interface......................................................................................... 5-1
PSTCLK Timing ...................................................................................................................... 5-2
Example JMP Instruction Output on PST/DDATA .................................................................. 5-5
Debug Programming Model .................................................................................................... 5-6
Address Attribute Trigger Register (AATR)............................................................................. 5-7
Address Breakpoint Registers (ABLR, ABHR)........................................................................ 5-9
Configuration/Status Register (CSR) .................................................................................... 5-10
Data Breakpoint/Mask Registers (DBR and DBMR) ............................................................. 5-12
Program Counter Breakpoint Register (PBR) ....................................................................... 5-13
Program Counter Breakpoint Mask Register (PBMR)........................................................... 5-13
Trigger Definition Register (TDR).......................................................................................... 5-14
BDM Serial Interface Timing ................................................................................................. 5-17
Receive BDM Packet ............................................................................................................ 5-18
Transmit BDM Packet ........................................................................................................... 5-18
BDM Command Format ........................................................................................................ 5-20
Command Sequence Diagram.............................................................................................. 5-21
RAREG/RDREG Command Format .......................................................................................... 5-22
RAREG/RDREG Command Sequence...................................................................................... 5-22
WAREG/WDREG Command Format ......................................................................................... 5-23
WAREG/WDREG Command Sequence .................................................................................... 5-23
READ Command/Result Formats ........................................................................................... 5-24
READ Command Sequence ................................................................................................... 5-24
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
v

5 Page





MCF5272 arduino
List of Figures (Continued)
Figure
Number
Title
Page
Number
20-4
20-5
20-6
20-7
20-8
20-9
20-10
20-11
20-12
20-13
20-14
20-15
20-16
20-17
20-18
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20-20
20-21
20-22
20-23
20-24
21-1
21-2
21-3
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21-5
21-6
21-7
21-8
22-1
22-2
23-1
23-2
23-3
23-4
23-5
23-6
23-7
23-8
23-9
23-10
23-11
Word Write; EBI = 00; 16-/32-Bit Port; Internal Termination ................................................. 20-9
Longword Read with Address Setup; EBI = 00; 32-Bit Port; Internal Termination................ 20-9
Longword Write with Address Setup; EBI = 00; 32-Bit Port; Internal Termination .............. 20-10
Longword Read with Address Hold; EBI = 00; 32-Bit Port; Internal Termination................ 20-10
Longword Write with Address Hold; EBI = 00; 32-Bit Port; Internal Termination ................ 20-11
Longword Read; EBI = 00; 32-Bit Port; Terminated by TA with One Wait State ................ 20-11
Longword Read; EBI=11; 32-Bit Port; Internal Termination................................................ 20-12
Word Write; EBI=11; 16/32-Bit Port; Internal Termination .................................................. 20-13
Read with Address Setup; EBI=11; 32-Bit Port; Internal Termination................................. 20-14
Longword Write with Address Setup; EBI=11; 32-Bit Port; Internal Termination ................ 20-14
Read with Address Hold; EBI=11; 32-Bit Port; Internal Termination................................... 20-15
Longword Write with Address Hold; EBI=11; 32-Bit Port; Internal Termination .................. 20-15
Longword Read with Address Setup and Address Hold;
EBI = 11; 32-Bit Port, Internal Termination ......................................................................... 20-16
Longword Write with Address Setup and Address Hold;
EBI = 11; 32-Bit Port, Internal Termination ......................................................................... 20-17
Example of a Misaligned Longword Transfer...................................................................... 20-18
Example of a Misaligned Word Transfer ............................................................................. 20-18
Longword Write Access To 32-Bit Port Terminated with TEA Timing................................. 20-20
Master Reset Timing ........................................................................................................... 20-22
Normal Reset Timing .......................................................................................................... 20-23
Software Watchdog Timer Reset Timing ............................................................................ 20-24
Soft Reset Timing ............................................................................................................... 20-25
Test Access Port Block Diagram........................................................................................... 21-2
TAP Controller State Machine............................................................................................... 21-3
Output Cell (O.Cell) (BC–1) .................................................................................................. 21-4
Input Cell (I.Cell). Observe only (BC–4)................................................................................ 21-5
Output Control Cell (En.Cell) (BC–4) .................................................................................... 21-5
Bidirectional Cell (IO.Cell) (BC–6)......................................................................................... 21-6
General Arrangement for Bidirectional Pins.......................................................................... 21-6
Bypass Register .................................................................................................................... 21-8
MCF5272 Pinout (196 MAPBGA) ......................................................................................... 22-1
196 MAPBGA Package Dimensions (Case No. 1128A-01) .................................................. 22-2
Clock Input Timing Diagram.................................................................................................. 23-5
General Input Timing Requirements ..................................................................................... 23-7
Read/Write SRAM Bus Timing.............................................................................................. 23-9
SRAM Bus Cycle Terminated by TA ................................................................................... 23-10
SRAM Bus Cycle Terminated by TEA................................................................................. 23-11
Reset and Mode Select/HIZ Configuration Timing.............................................................. 23-12
Real-Time Trace AC Timing................................................................................................ 23-13
BDM Serial Port AC Timing................................................................................................. 23-13
SDRAM Signal Timing ........................................................................................................ 23-15
SDRAM Self-Refresh Cycle Timing .................................................................................... 23-16
MII Receive Signal Timing Diagram.................................................................................... 23-17
MCF5272 ColdFire® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
xi

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