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PDF IS61QDB42M36A Data sheet ( Hoja de datos )
| Número de pieza | IS61QDB42M36A | |
| Descripción | 72Mb QUAD (Burst 4) SYNCHRONOUS SRAM | |
| Fabricantes | ISSI | |
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IS61QDB44M18A
IS61QDB42M36A
4Mx18, 2Mx36
72Mb QUAD (Burst 4) SYNCHRONOUS SRAM
FEATURES
DESCRIPTION
AUGUST 2014
2Mx36 and 4Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data
valid window.
Separate independent read and write ports with
concurrent read and write operations.
Synchronous pipeline read with late write operation.
Double Data Rate (DDR) interface for read and
write input ports.
1.5 cycle read latency.
Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control
registering at rising edges only.
Two output clocks (C and C#) for data output control.
Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data.
+1.8V core power supply and 1.5, 1.8V VDDQ, used
with 0.75, 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte
writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1
functions.
Byte write capability.
Fine ball grid array (FBGA) package:
13mmx15mm and 15mmx17mm body size
165-ball (11 x 15) array
Programmable impedance output drivers via 5x
user-supplied precision resistor.
The 72Mb IS61QDB42M36A and IS61QDB44M18A are
synchronous, high-performance CMOS static random access
memory (SRAM) devices. These SRAMs have separate I/Os,
eliminating the need for high-speed bus turnaround. The
rising edge of K clock initiates the read/write operation, and
all internal operations are self-timed. Refer to the Timing
Reference Diagram for Truth Table for a description of the
basic operations of these QUAD (Burst of 4) SRAMs.
Read and write addresses are registered on alternating rising
edges of the K clock. Reads and writes are performed in
double data rate. The following are registered internally on
the rising edge of the K clock:
Read/write address
Read enable
Write enable
Byte writes for burst addresses 1 and 3
Data-in for burst addresses 1 and 3
The following are registered on the rising edge of the K#
clock:
Byte writes for burst addresses 2 and 4
Data-in for burst addresses 2 and 4
Byte writes can change with the corresponding data-in to
enable or disable writes on a per-byte basis. An internal write
buffer enables the data-ins to be registered one cycle after
the write address. The first data-in burst is clocked one cycle
later than the write command signal, and the second burst is
timed to the following rising edge of the K# clock. Two full
clock cycles are required to complete a write operation.
During the burst read operation, the data-outs from the first
and third bursts are updated from output registers of the
second and third rising edges of the C# clock (starting 1.5
cycles later after read command). The data-outs from the
second and fourth bursts are updated with the third and
fourth rising edges of the C clock. The K and K# clocks are
used to time the data-outs whenever the C and C# clocks are
tied high. Two full clock cycles are required to complete a
read operation.
The device is operated with a single +1.8V power supply and
is compatible with HSTL I/O interfaces.
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
08/21/2014
1
1 page  
IS61QDB44M18A
IS61QDB42M36A
The data-in provided for writing is initially kept in write buffers. The information in these buffers is written into the array
on the third write cycle. A read cycle to the last two write addresses produces data from the write buffers. The SRAM
maintains data coherency.
During a write, the byte writes independently control which byte of any of the four burst addresses is written (see
X18/X36 Write Truth Tables and Timing Reference Diagram for Truth Table).
Whenever a write is disabled (W# is high at the rising edge of K), data is not written into the memory.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust
its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the
SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range of RQ to guarantee
impedance matching is between 175Ω and 350Ω at VDDQ=1.5V. The RQ resistor should be placed less than two inches
away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 7.5pF.
The ZQ pin can also be directly connected to VDDQ to obtain a minimum impedance setting. ZQ should not be
connected to VSS.
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in
supply voltage and temperature. During power-up, the driver impedance is in the middle of allowable impedances
values. The final impedance value is achieved within 1024 clock cycles.
Clock Consideration
This device uses an internal DLL for maximum output data valid window. It can be placed in a stopped-clock mode to
minimize power and requires only 1024 cycles to restart.
No clocks can be issued until VDD reaches its allowable operating range.
Single Clock Mode
This device can be also operated in single-clock mode. In this case, C and C# are both connected high at power-up
and must never change. Under this condition, K and K# will control the output timings.
Either clock pair must have both polarities switching and must never connect to VREF, as they are not differential
clocks.
Depth Expansion
Separate input and output ports enable easy depth expansion, as each port can be selected and deselected
independently. Read and write operations can occur simultaneously without affecting each other. Also, all pending
read and write transactions are always completed prior to deselecting the corresponding port.
Delay Locked Loop (DLL)
Delay Locked Loop (DLL) is a new system to align the output data coincident with clock rising or falling edge to
enhance the output valid timing characteristics. It is locked to the clock frequency and is constantly adjusted to match
the clock frequency. Therefore device can have stable output over the temperature and voltage variation.
DLL has a limitation of locking range and jitter adjustment which are specified as tKHKH and tKCvar respectively in the
AC timing characteristics. In order to turn this feature off, applying logic low to the Doff# pin will bypass this. In the DLL
off mode, the device behaves with one cycle latency and a longer access time which is known in DDR-I or legacy
QUAD mode.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
08/21/2014
5
5 Page 
IS61QDB44M18A
IS61QDB42M36A
Clock Truth Table
(Use the following table with the Timing Reference Diagram for Truth Table.)
Mode
Clock Controls
K R# W#
Stop Clock
No
Operation
(NOP)
Read A
Stop
L→H
L→H
X
H
L
X
H
X
Write B L → H X L
DB
Previous
State
X
X
DIN at K
(t+2.0)
Data In
DB+1
Previous
State
DB+2
Previous
State
XX
X
DIN at K#
(t+2.5)
X
DIN at K
(t+3.0)
DB+3
Previous
State
X
X
DIN at K#
(t+3.5)
QA
Previous
State
High-Z
DOUT at C#
(t+1.5)
X
Data Out
QA+1
Previous
State
QA+2
Previous
State
High-Z
High-Z
DOUT at C
(t+2.0)
X
DOUT at C#
(t+2.5)
X
QA+3
Previous
State
High-Z
DOUT at C
(t+3.0)
X
Notes:
1. Internal burst counter is always fixed as four-bit.
2. X = “don’t care”; H = logic “1”; L = logic “0”.
3. A read operation is started when control signal R# is active low
4. A write operation is started when control signal W# is active low.
5. Before entering into stop clock, all pending read and write commands must be completed.
6. Consecutive read or write operations can be started only at every other K clock rising edge. If two read or write operations are issued in
consecutive K clock rising edges, the second one will be ignored.
7. If both R# and W# are active low after a NOP operation, the write operation will be ignored.
8. For timing definitions, refer to the AC Timing Characteristics table. Signals must meet AC specifications at timings indicated in parenthesis with
respect to switching clocks K, K#, C and C#.
x18 Write Truth Table
(Use the following table with the Timing Reference Diagram for Truth Table.)
Operation
Write Byte 0
Write Byte 1
Write All Bytes
Abort Write
Write Byte 0
Write Byte 1
Write All Bytes
Abort Write
Write Byte 0
Write Byte 1
Write All Bytes
Abort Write
Write Byte 0
Write Byte 1
Write All Bytes
Abort Write
K (t+1.0)
L→H
L→H
L→H
L→H
K# (t+1.5)
L→H
L→H
L→H
L→H
K (t+2.0)
L→H
L→H
L→H
L→H
K# (t+2.5)
L→H
L→H
L→H
L→H
BW0#
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
BW1#
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
DB
D0-8 (t+2.0)
D9-17 (t+2.0)
D0-17 (t+2.0)
Don't Care
DB+1
D0-8 (t+2.5)
D9-17 (t+2.5)
D0-17 (t+2.5)
Don't Care
DB+2
D0-8 (t+3.0)
D9-17 (t+3.0)
D0-17 (t+3.0)
Don't Care
DB+3
D0-8 (t+3.5)
D9-17 (t+3.5)
D0-17 (t+3.5)
Don't Care
Notes:
1. For all cases, W# needs to be active low during the rising edge of K occurring at time t.
2. For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and
K#.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
08/21/2014
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IS61QDB42M36A.PDF ] | |
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