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IS61QDB41M18A の電気的特性と機能

IS61QDB41M18AのメーカーはISSIです、この部品の機能は「18Mb QUAD (Burst 4) SYNCHRONOUS SRAM」です。


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部品番号 IS61QDB41M18A
部品説明 18Mb QUAD (Burst 4) SYNCHRONOUS SRAM
メーカ ISSI
ロゴ ISSI ロゴ 




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IS61QDB41M18A Datasheet, IS61QDB41M18A PDF,ピン配置, 機能
IS61QDB41M18A
IS61QDB451236A
1Mx18, 512Kx36
18Mb QUAD (Burst 4) SYNCHRONOUS SRAM
FEATURES
DESCRIPTION
OCTOBER 2014
512Kx36 and 1Mx18 configuration available.
On-chip Delay-Locked loop (DLL) for wide data valid
window.
Separate independent read and write ports with
concurrent read and write operations.
Synchronous pipeline read with late write operation.
Double Data Rate (DDR) interface for read and
write input ports.
1.5 cycle read latency.
Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control
registering at rising edges only.
Two output clocks (C and C#) for data output control.
Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data.
+1.8V core power supply and 1.5, 1.8V VDDQ, used
with 0.75, 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte
writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1
functions.
Byte write capability.
Fine ball grid array (FBGA) package:
13mmx15mm and 15mmx17mm body size
165-ball (11 x 15) array
Programmable impedance output drivers via 5x
user-supplied precision resistor.
The 18Mb IS61QDB451236A and IS61QDB41M18A are
synchronous, high-performance CMOS static random access
memory (SRAM) devices. These SRAMs have separate I/Os,
eliminating the need for high-speed bus turnaround. The
rising edge of K clock initiates the read/write operation, and
all internal operations are self-timed. Refer to the Timing
Reference Diagram for Truth Table for a description of the
basic operations of these QUAD (Burst of 4) SRAMs.
Read and write addresses are registered on alternating rising
edges of the K clock. Reads and writes are performed in
double data rate. The following are registered internally on
the rising edge of the K clock:
Read/write address
Read enable
Write enable
Byte writes for burst addresses 1 and 3
Data-in for burst addresses 1 and 3
The following are registered on the rising edge of the K#
clock:
Byte writes for burst addresses 2 and 4
Data-in for burst addresses 2 and 4
Byte writes can change with the corresponding data-in to
enable or disable writes on a per-byte basis. An internal write
buffer enables the data-ins to be registered one cycle after
the write address. The first data-in burst is clocked one cycle
later than the write command signal, and the second burst is
timed to the following rising edge of the K# clock. Two full
clock cycles are required to complete a write operation.
During the burst read operation, the data-outs from the first
and third bursts are updated from output registers of the
second and third rising edges of the C# clock (starting 1.5
cycles later after read command). The data-outs from the
second and fourth bursts are updated with the third and
fourth rising edges of the C clock. The K and K# clocks are
used to time the data-outs whenever the C and C# clocks are
tied high. Two full clock cycles are required to complete a
read operation.
The device is operated with a single +1.8V power supply and
is compatible with HSTL I/O interfaces.
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/02/2014
1

1 Page





IS61QDB41M18A pdf, ピン配列
IS61QDB41M18A
IS61QDB451236A
Ball Descriptions
Symbol
K, K#
C, C#
CQ, CQ#
Doff#
SA
D0 - Dn
Q0 - Qn
W#
R#
BWx#
VREF
VDD
VDDQ
VSS
ZQ
TMS, TDI, TCK
Type
Input
Input
Output
Input
Input
Input
Output
Input
Input
Input
Input
reference
Power
Power
Ground
Input
Input
Description
Input clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising
edges. These balls cannot remain VREF level.
Input clock for output data. C and C# are used to clock out the READ data. They can be used
together to deskew the flight times of various devices on the board back to the controller. See
application example for further details.
Synchronous echo clock outputs: The edges of these outputs are tightly matched to the
synchronous data outputs and can be used as a data valid indication. These signals are free
running clocks and do not stop when Q tri-states.
DLL disable and reset input : when low, this input causes the DLL to be bypassed and reset the
previous DLL information. When high, DLL will start operating and lock the frequency after tCK lock
time. The device behaves in one read latency mode when the DLL is turned off. In this mode, the
device can be operated at a frequency of up to 167 MHz.
Synchronous address inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. These inputs are ignored when device is deselected.
Synchronous data inputs: Input data must meet setup and hold times around the rising edges of K
and K# during WRITE operations. See BALL CONFIGURATION figures for ball site location of
individual signals.
The x18 device uses D0~D17. D18~D35 should be treated as NC pin.
The x36 device uses D0~D35.
Synchronous data outputs: Output data is synchronized to the respective C and C#, or to the
respective K and K# if C and /C are tied to high. This bus operates in response to R# commands.
See BALL CONFIGURATION figures for ball site location of individual signals.
The x18 device uses Q0~Q17. Q18~Q35 should be treated as NC pin.
The x36 device uses Q0~Q35.
Synchronous write: When low, this input causes the address inputs to be registered and a WRITE
cycle to be initiated. This input must meet setup and hold times around the rising edge of K.
Synchronous read: When low, this input causes the address inputs to be registered and a READ
cycle to be initiated. This input must meet setup and hold times around the rising edge of K.
Synchronous byte writes: When low, these inputs cause their respective byte to be registered and
written during WRITE cycles. These signals are sampled on the same edge as the corresponding
data and must meet setup and hold times around the rising edges of K and #K for each of the two
rising edges comprising the WRITE cycle. See Write Truth Table for signal to data relationship.
HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve system noise
margin. Provides a reference voltage for the HSTL input buffers.
Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.
Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating
Conditions for range.
Ground of the device
Output impedance matching input: This input is used to tune the device outputs to the system data
bus impedance. Q and CQ output impedance are set to 0.2xRQ, where RQ is a resistor from this
ball to ground. This ball can be connected directly to VDDQ, which enables the minimum
impedance mode. This ball cannot be connected directly to VSS or left unconnected.
IEEE1149.1 input pins for JTAG.
TDO
NC
Output
N/A
IEEE1149.1 output pins for JTAG.
No connect: These signals should be left floating or connected to ground to improve package heat
dissipation.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/02/2014
3


3Pages


IS61QDB41M18A 電子部品, 半導体
IS61QDB41M18A
IS61QDB451236A
The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K#
for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is
not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being
reset, it gets locked after 2048 cycles of stable clock.
Power-Up and Power-Down Sequences
The recommendation of voltage apply sequence is : VDD VDDQ 1)VREF2)VIN
Notes: VDDQ can be applied concurrently with VDD.
VREF can be applied concurrently with VDDQ.
After power and clock signals are stabilized, device can be ready for normal operation after tKC-Lock cycles. In tKC-
lock cycle period, device initializes internal logics and locks DLL. Depending on /Doff status, locking DLL will be
skipped. The following timing pictures are possible examples of power up sequence.
Please note all inputs including clocks must be either logically High or Low during Power On stage.
Sequence1. /Doff is fixed low
After tKC-lock cycle of stable clock, device is ready for normal operation.
Power On stage Unstable Clock Period
Stable Clock period
Read to use
K
K#
VDD
VDDQ
>tKC-lock for device initialization
VREF
VIN
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only
one of cases.
Sequence2. /Doff is controlled and goes high after clock being stable.
Power On stage
Unstable Clock Period
Stable Clock period
Read to use
K
K#
Doff#
VDD
>tKC-lock for device initialization
VDDQ
VREF
VIN
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only
one of cases.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/02/2014
6

6 Page



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部品番号部品説明メーカ
IS61QDB41M18A

18Mb QUAD (Burst 4) SYNCHRONOUS SRAM

ISSI
ISSI


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