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PDF IS61QDB22M18A Data sheet ( Hoja de datos )
| Número de pieza | IS61QDB22M18A | |
| Descripción | 36Mb QUAD (Burst 2) Synchronous SRAM | |
| Fabricantes | ISSI | |
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IS61QDB22M18A
IS61QDB21M36A
2Mx18, 1Mx36
36Mb QUAD (Burst 2) Synchronous SRAM
JANUARY 2015
FEATURES
1Mx36 and 2Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data
valid window.
Separate independent read and write ports with
concurrent read and write operations.
Synchronous pipeline read with EARLY write
operation.
Double Data Rate (DDR) interface for read and
write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control
registering at rising edges only.
Two output clocks (C and C#) for data output control.
Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data.
+1.8V core power supply and 1.5, 1.8V VDDQ, used
with 0.75, 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte
writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1
functions.
Byte write capability.
Fine ball grid array (FBGA) package:
13mmx15mm and 15mmx17mm body size
165-ball (11 x 15) array
Programmable impedance output drivers via 5x
user-supplied precision resistor.
DESCRIPTION
The Mb and are
synchronous, high-performance CMOS static random access
memory (SRAM) devices. These SRAMs have separate I/Os,
eliminating the need for high-speed bus turnaround. The
rising edge of K clock initiates the read/write operation, and
all internal operations are self-timed. Refer to the
for a description of the
basic operations of these
SRAMs.
The input address bus operates at double data rate. The
following are registered internally on the rising edge of the K
clock:
Read address
Read enable
Write enable
Byte writes
Data-in for early writes
The following are registered on the rising edge of the K#
clock:
Write address
Byte writes
Data-in for second burst addresses
Byte writes can change with the corresponding data-in to
enable or disable writes on a per-byte basis. An internal write
buffer enables the data-ins to be registered half a cycle
earlier than the write address. The first data-in burst is
clocked at the same time as the write command signal, and
the second burst is timed to the following rising edge of the
K# clock.
During the burst read operation, the data-outs from the first
bursts are updated from output registers of the second rising
edge of the C# clock (starting 1.5 cycles later after read
command). The data-outs from the second bursts are
updated with the third rising edge of the C clock. The K and
K# clocks are used to time the data-outs whenever the C and
C# clocks are tied high.
The device is operated with a single +1.8V power supply and
is compatible with HSTL I/O interfaces.
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/02/2014
1
1 page  
IS61QDB22M18B
IS61QDB21M36B
During a write, the byte writes independently control which byte of any of the four burst addresses is written (see
X18/X36 Write Truth Tables and Timing Reference Diagram for Truth Table).
Whenever a write is disabled (W# is high at the rising edge of K), data is not written into the memory.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust
its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the
SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range of RQ to guarantee
impedance matching is between 175Ω and 350Ω with VDDQ=1.5V. The RQ resistor should be placed less than two
inches away from the ZQ ball on the SRAM module. The capacitance of the loaded ZQ trace must be less than 7.5pF.
The ZQ pin can also be directly connected to VDDQ to obtain a minimum impedance setting. ZQ must never be
connected to VSS.
PROGRAMMABLE IMPEDANCE AND POWER-UP REQUIREMENTs
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in
supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable impedances values.
The final impedance value is achieved within 1024 clock cycles.
Single Clock Mode
This device can be also operated in single-clock mode. In this case, C and C# are both connected high at power-up
and must never change. Under this condition, K and K# will control the output timings.
Either clock pair must have both polarities switching and must never connect to VREF, as they are not differential
clocks.
Depth Expansion
Separate input and output ports enable easy depth expansion, as each port can be selected and deselected
independently. Read and write operations can occur simultaneously without affecting each other. Also, all pending
read and write transactions are always completed prior to deselecting the corresponding port.
Delay Locked Loop (DLL)
Delay Locked Loop (DLL) is a new system to align the output data coincident with clock rising or falling edge to
enhance the output valid timing characteristics. It is locked to the clock frequency and is constantly adjusted to match
the clock frequency. Therefore device can have stable output over the temperature and voltage variation.
DLL has a limitation of locking range and jitter adjustment which are specified as tKHKH and tKCvar respectively in the
AC timing characteristics. In order to turn this feature off, applying logic low to the Doff# pin will bypass this. In the DLL
off mode, the device behaves with 1.0 cycle latency and a longer access time which is known in DDR-I or old QUAD
mode.
The DLL can also be reset without power down by toggling Doff# pin low to high or stopping the input clocks K and K#
for a minimum of 30ns.(K and K# must be stayed either at higher than VIH or lower than VIL level. Remaining Vref is
not permitted.) DLL reset must be issued when power up or when clock frequency changes abruptly. After DLL being
reset, it gets locked after 2048 cycles of stable clock.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/02/2014
5
5 Page 
IS61QDB22M18B
IS61QDB21M36B
x18 WRITE TRUTH TABLE
(Use the following table with the Timing Reference Diagram for Truth Table.)
Operation
Write Byte 0
Write Byte 1
Write All Bytes
Abort Write
Write Byte 0
Write Byte 1
Write All Bytes
Abort Write
K (t)
L→H
L→H
L→H
L→H
K# (t+0.5)
L→H
L→H
L→H
L→H
BW0#
L
H
L
H
L
H
L
H
BW1#
H
L
L
H
H
L
L
H
DB
D0-8 (t)
D9-17 (t)
D0-17 (t)
Don't Care
DB+1
D0-8 (t+0.5)
D9-17 (t+0.5)
D0-17 (t+0.5)
Don't Care
Notes:
1. Refer to the Timing Reference Diagram for Truth Table. Cycle time starts at n and is referenced to the K clock.
2. For all cases, W# needs to be active low during the rising edge of K occurring at time t.
3. For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and K#.
x36 WRITE TRUTH TABLE
(Use the following table with the Timing Reference Diagram for Truth Table.)
Operation
K (t)
K# (t+0.5)
BW0#
BW1#
BW2#
Write Byte 0
L→H
L HH
BW3#
H
DB
D0-8 (t)
DB+1
Write Byte 1
L→H
H L H H D9-17 (t)
Write Byte 2
L→H
H H L H D18-26 (t)
Write Byte 3
L→H
H H H L D27-35 (t)
Write All Bytes
L→H
L L L L D0-35 (t)
Abort Write
L→H
H H H H Don't Care
Write Byte 0
L→H
L
H HH
D0-8 (t+0.5)
Write Byte 1
L→H
H
L HH
D9-17 (t+0.5)
Write Byte 2
L→H
H
H LH
D18-26 (t+0.5)
Write Byte 3
L→H
H
H HL
D27-35 (t+0.5)
Write All Bytes
L→H
L
L LL
D0-35 (t+0.5)
Abort Write
L→H
H
H HH
Don't Care
Notes:
1. For all cases, W# needs to be active low during the rising edge of K occurring at time t.
2. For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and K#.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/02/2014
11
11 Page | ||
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| PDF Descargar | [ Datasheet IS61QDB22M18A.PDF ] | |
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