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PDF IS65WV10248EBLL Data sheet ( Hoja de datos )
| Número de pieza | IS65WV10248EBLL | |
| Descripción | ULTRA LOW POWER CMOS STATIC RAM | |
| Fabricantes | ISSI | |
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IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
1Mx8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
NOVEMBER 2014
KEY FEATURES
High-speed access time: 45ns, 55ns
CMOS low power operation
– 36 mW (typical) operating
– 12 µW (typical) CMOS standby
TTL compatible interface levels
Single power supply
–1.65V-2.2V VDD (62/65WV10248EALL)
– 2.2V-3.6V VDD (62/65WV10248EBLL)
Data control for upper and lower bytes
Automotive temperature (-40oC to +125oC)
Lead-free available
BLOCK DIAGRAM
DESCRIPTION
The ISSI IS62WV10248EALL/ IS62WV10248EBLL are
high-speed, 8M bit static RAMs organized as 1M words
by 8 bits. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process
coupled with innovative circuit design techniques,
yields high-performance and low power consumption
devices.
When is HIGH (deselected) or when CS2 is low
(deselected), the device assumes a standby mode at
which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip
Enable and Output Enable inputs. The active LOW
Write Enable ( ) controls both writing and reading of
the memory.
The IS62WV10248EALL and IS62WV10248EBLL are
packaged in the JEDEC standard 48-pin mini BGA
(6mm x 8mm) and 44-Pin TSOP (TYPE II).
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/21/2014
1
1 page  
IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
ELECTRICAL CHARACTERISTICS
IS62(5)WV10248EALL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE)
Symbol
VOH
VOL
VIH(1)
VIL(1)
ILI
ILO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
Test Conditions
IOH = -0.1 mA
IOL = 0.1 mA
GND < VIN < VDD
GND < VIN < VDD, Output Disabled
Min.
1.4
—
1.4
–0.2
–1
–1
Max.
—
0.2
VDD + 0.2
0.4
1
1
Unit
V
V
V
V
µA
µA
Notes:
1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested.
IS62(5)WV10248EBLL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE)
Symbol
VOH
Parameter
Output HIGH Voltage
VOL
VIH(1)
VIL(1)
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
ILI Input Leakage
ILO Output Leakage
Test Conditions
2.2 ≤ VDD < 2.7, IOH = -0.1 mA
2.7 ≤ VDD ≤ 3.6, IOH = -1.0 mA
2.2 ≤ VDD < 2.7, IOL = 0.1 mA
2.7 ≤ VDD ≤ 3.6, IOL = 2.1 mA
2.2 ≤ VDD < 2.7
2.7 ≤ VDD ≤ 3.6
2.2 ≤ VDD < 2.7
2.7 ≤ VDD ≤ 3.6
GND < VIN < VDD
GND < VIN < VDD, Output Disabled
Min.
2.0
2.4
—
—
1.8
2.2
–0.3
–0.3
–1
–1
Max.
—
—
0.4
0.4
VDD + 0.3
VDD + 0.3
0.6
0.8
1
1
Unit
V
V
V
V
V
V
V
V
µA
µA
Notes:
1. VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/21/2014
5
5 Page 
IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
WRITE CYCLE NO. 3 ( CONTROLLED: IS LOW DURING WRITE CYCLE)
Notes:
If is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous
READ operation will drive IO BUS.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/21/2014
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet IS65WV10248EBLL.PDF ] | |
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