|
|
PDF IS64WV51216EDBLL Data sheet ( Hoja de datos )
| Número de pieza | IS64WV51216EDBLL | |
| Descripción | 512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM | |
| Fabricantes | ISSI | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IS64WV51216EDBLL (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
|
No Preview Available !
IS61WV51216EDALL
IS61/64WV51216EDBLL
512K x 16 HIGH-SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH ECC
FEBRUARY 2013
FEATURES
• High-speed access times: 8, 10, 20 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for greater
noise immunity
• Easy memory expansion with CE and OE options
• CE power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single Power Supply
– Vdd = 1.65V to 2.2V (IS61WV51216EDALL)
– Vdd = 2.4V to 3.6V (IS61/64WV51216EDBLL)
• Packages available:
– 48-ball miniBGA (6mm x 8mm)
– 44-pin TSOP (Type II)
• Industrial and Automotive Temperature Support
• Lead-free available
• Data control for upper and lower bytes
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ISSI IS61WV51216EDALL and
IS61/64WV51216EDBLL are high-speed, 8M-bit static
RAMs organized as 512K words by 16 bits. It is fabri-
cated using ISSI's high-performance CMOS technology.
This highly reliable process coupled with innovative
circuit design techniques, yields high-performance and
low power consumption devices.
When CE is HIGH (deselected), the device assumes
a standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip En-
able and Output Enable inputs, CE and OE. The active
LOW Write Enable (WE) controls both writing and read-
ing of the memory. A data byte allows Upper Byte (UB)
and Lower Byte (LB) access.
The device is packaged in the JEDEC standard 44-pin
TSOP Type II and 48-pin Mini BGA (6mm x 8mm).
A0-A18
Decoder
Memory
Lower IO
Array-
512Kx8
ECC
Array-
512K
x4
Memory
Upper IO
Array-
512Kx8
ECC
Array-
512K
x4
IO0-7
IO8-15
8
8 8 12
8
I/O Data
Circuit
8
ECC
12
ECC
48
Column I/O
4
/CE
/OE Control
/WE Circuit
/UB
/LB
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. A
02/20/2013
1 page  
IS61WV51216EDALL
IS61/64WV51216EDBLL
OPERATING RANGE (Vdd)
Range Ambient
Temperature
Industrial
–40°C to +85°C
Automotive (A1) –40°C to +85°C
Automotive (A3) –40°C to +125°C
IS61WV51216EDALL
Vdd (20ns)
1.65V-2.2V
—
—
IS61WV51216EDBLL
Vdd (8, 10ns)
2.4V-3.6V
—
—
IS64WV51216EDBLL
Vdd (10ns)
—
2.4V-3.6V
2.4V-3.6V
ERROR DETECTION AND ERROR CORRECTION
• Independent ECC for each byte
• Detect and correct one bit error per byte
• Better reliability than parity code schemes which can only detect an error but not correct an error
• Backward Compatible: Drop in replacement to current in industry standard devices (without ECC)
Integrated Silicon Solution, Inc. — www.issi.com 5
Rev. A
02/20/2013
5 Page 
IS61WV51216EDALL
IS61/64WV51216EDBLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 -10
Symbol Parameter Min. Max. Min. Max. Unit
twc
Write Cycle Time
8
—
10 —
ns
tsce
CE to Write End
6.5 —
8
—
ns
taw
Address Setup Time
to Write End
6.5 —
8
—
ns
tha
Address Hold from Write End
0
—
0
—
ns
tsa
Address Setup Time
0
—
0
—
ns
tpwb
LB, UB Valid to End of Write
6.5 —
8
—
ns
tpwe1 WE Pulse Width
6.5 —
8
—
ns
tpwe2 WE Pulse Width (OE = LOW)
8.0 —
10 —
ns
tsd
Data Setup to Write End
5
—
6
—
ns
thd
Data Hold from Write End
0
—
0
—
ns
thzwe(2) WE LOW to High-Z Output
— 3.5
—
5
ns
tlzwe(2) WE HIGH to Low-Z Output
2
—
2
—
ns
Notes:
1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initi-
ate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising
or falling edge of the signal that terminates the write. Shaded area product in development
Integrated Silicon Solution, Inc. — www.issi.com 11
Rev. A
02/20/2013
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet IS64WV51216EDBLL.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IS64WV51216EDBLL | 512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM | ISSI |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |