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IS61WV51216EDALL の電気的特性と機能

IS61WV51216EDALLのメーカーはISSIです、この部品の機能は「512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS61WV51216EDALL
部品説明 512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM
メーカ ISSI
ロゴ ISSI ロゴ 




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IS61WV51216EDALL Datasheet, IS61WV51216EDALL PDF,ピン配置, 機能
IS61WV51216EDALL
IS61/64WV51216EDBLL
512K x 16 HIGH-SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH ECC
FEBRUARY 2013
FEATURES
• High-speed access times: 8, 10, 20 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for greater
noise immunity
Easy memory expansion with CE and OE options
CE power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single Power Supply
– Vdd = 1.65V to 2.2V (IS61WV51216EDALL)
– Vdd = 2.4V to 3.6V (IS61/64WV51216EDBLL)
• Packages available:
48-ball miniBGA (6mm x 8mm)
– 44-pin TSOP (Type II)
• Industrial and Automotive Temperature Support
• Lead-free available
• Data control for upper and lower bytes
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ISSI IS61WV51216EDALL and
IS61/64WV51216EDBLL are high-speed, 8M-bit static
RAMs organized as 512K words by 16 bits. It is fabri-
cated using ISSI's high-performance CMOS technology.
This highly reliable process coupled with innovative
circuit design techniques, yields high-performance and
low power consumption devices.
When CE is HIGH (deselected), the device assumes
a standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip En-
able and Output Enable inputs, CE and OE. The active
LOW Write Enable (WE) controls both writing and read-
ing of the memory. A data byte allows Upper Byte (UB)
and Lower Byte (LB) access.
The device is packaged in the JEDEC standard 44-pin
TSOP Type II and 48-pin Mini BGA (6mm x 8mm).
A0-A18
Decoder
Memory
Lower IO
Array-
512Kx8
ECC
Array-
512K
x4
Memory
Upper IO
Array-
512Kx8
ECC
Array-
512K
x4
IO0-7
IO8-15
8
8 8 12
8
I/O Data
Circuit
8
ECC
12
ECC
48
Column I/O
4
/CE
/OE Control
/WE Circuit
/UB
/LB
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. A
02/20/2013

1 Page





IS61WV51216EDALL pdf, ピン配列
IS61WV51216EDALL
IS61/64WV51216EDBLL
PIN CONFIGURATIONS
44-Pin TSOP (Type II)
A0 1
A1 2
A2 3
A3 4
A4 5
CE 6
I/O0 7
I/O1 8
I/O2 9
I/O3 10
VDD 11
GND 12
I/O4 13
I/O5 14
I/O6 15
I/O7 16
WE 17
A5 18
A6 19
A7 20
A8 21
A9 22
44 A17
43 A16
42 A15
41 OE
40 UB
39 LB
38 I/O15
37 I/O14
36 I/O13
35 I/O12
34 GND
33 VDD
32 I/O11
31 I/O10
30 I/O9
29 I/O8
28 A18
27 A14
26 A13
25 A12
24 A11
23 A10
PIN DESCRIPTIONS
A0-A18
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
CE Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)
NC No Connection
Vdd Power
GND
Ground
Integrated Silicon Solution, Inc. — www.issi.com 3
Rev. A
02/20/2013


3Pages


IS61WV51216EDALL 電子部品, 半導体
IS61WV51216EDALL
IS61/64WV51216EDBLL
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 2.4V-3.6V
Symbol Parameter
Test Conditions
Voh
Vol
Output HIGH Voltage
Output LOW Voltage
Vdd = Min., Ioh = –1.0 mA
Vdd = Min., Iol = 1.0 mA
Vih
Input HIGH Voltage
Vil
Input LOW Voltage(1)
Ili
Input Leakage
GND Vin Vdd
Ilo
Output Leakage
GND Vout Vdd, Outputs Disabled
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 2 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 2 ns). Not 100% tested.
Min. Max. Unit
1.8 —
V
— 0.4 V
2.0 Vdd + 0.3 V
–0.3
0.8
V
–1 1 µA
–1 1 µA
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 1.65V-2.2V
Symbol Parameter
Test Conditions
Min.
Max.
Unit
Voh
Output HIGH Voltage Ioh = -0.1 mA
1.4 — V
Vol
Output LOW Voltage
Iol = 0.1 mA
— 0.2 V
Vih
Input HIGH Voltage
1.4
Vdd + 0.2
V
Vil
Input LOW Voltage
–0.2 0.4 V
Ili
Input Leakage
GND Vin Vdd
–1 1 µA
Ilo
Output Leakage
GND Vout Vdd, –1
1 µA
Outputs Disabled
Notes:
1. Vil (min.) = –0.3V DC; Vil (min.) = –1.0V AC (pulse width < 2 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 1.0V AC (pulse width < 2 ns). Not 100% tested.
6 Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/20/2013

6 Page



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部品番号部品説明メーカ
IS61WV51216EDALL

512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM

ISSI
ISSI


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