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PDF IS61WV25632ALL Data sheet ( Hoja de datos )

Número de pieza IS61WV25632ALL
Descripción 256K x 32 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM
Fabricantes ISSI 
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IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
256K x 32 HIGH-SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
PRELIMINARY INFORMATION
APRIL 2008
FEATURES
• High-speed access times:
8, 10, 20 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE op-
tions
CE power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single power supply
Vdd 1.65V to 2.2V (IS61WV25632Axx)
speed = 20ns for Vdd 1.65V to 2.2V
Vdd 2.4V to 3.6V (IS61/64WV25632Bxx)
speed = 10ns for Vdd 2.4V to 3.6V
speed = 8ns for Vdd 3.3V + 5%
• Packages available:
90-ball miniBGA (8mm x 13mm)
• Industrial and Automotive Temperature Support
• Lead-free available
DESCRIPTION
The ISSI IS61WV25632Axx/Bxx and IS64WV25632Bxx
are high-speed, 8M-bit static RAMs organized as 256K
words by 32 bits. It is fabricated using ISSI's high-per-
formance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields
high-performance and low power consumption devices.
When CE is HIGH (deselected), the device assumes
a standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of
the memory.
The device is packaged in the JEDEC standard 90-ball
BGA (8mm x 13mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A17
VDD
VSS
DQa-d
DECODER
I/O
DATA
CIRCUIT
256K x 32
MEMORY ARRAY
COLUMN I/O
CE
OE
WE
BWa-d
CE2
CONTROL
CIRCUIT
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  00B
04/23/08
1

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IS61WV25632ALL pdf
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
HIGH SPEED
OPERATING RANGE (Vdd) (IS61WV25632ALL)
Range
Ambient Temperature
Vdd
Commercial
0°C to +70°C
1.65V-2.2V
Industrial
–40°C to +85°C
1.65V-2.2V
Automotive –40°C to +125°C
1.65V-2.2V
Speed
20ns
20ns
20ns
OPERATING RANGE (Vdd) (IS61WV25632BLL)(1)
Range
Ambient Temperature
Vdd (8 ns)1
Vdd (10 ns)1
Commercial
0°C to +70°C
3.3V + 5%
2.4V-3.6V
Industrial
–40°C to +85°C
3.3V + 5%
2.4V-3.6V
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%,
the device meets 8ns.
OPERATING RANGE (Vdd) (IS64WV25632BLL)
Range
Ambient Temperature
Vdd (10 ns)
Automotive –40°C to +125°C
2.4V-3.6V
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8
Symbol Parameter
Test Conditions Min. Max.
Icc Vdd Dynamic Operating Vdd = Max.,
Supply Current
Iout = 0 mA, f = fmax
Com. — 110
Ind. — 115
Auto. — —
typ.(2)
Icc1 Operating
Vdd = Max.,
Supply Current
Iout = 0 mA, f = 0
Com. — 85
Ind. — 90
Auto. — —
Isb1 TTL Standby Current
(TTL Inputs)
Vdd = Max.,
Vin = Vih or Vil
CE Vih, f = 0
Com. — 30
Ind. — 35
Auto. — —
Isb2 CMOS Standby
Current (CMOS Inputs)
Vdd = Max.,
CE Vdd – 0.2V,
Vin Vdd – 0.2V, or
Vin 0.2V, f = 0
Com. — 20
Ind. — 25
Auto. — —
typ.(2)
-10
Min. Max.
— 90
— 95
— 140
60
— 85
— 90
— 110
— 30
— 35
— 70
— 20
— 25
— 60
4
-20
Min. Max. Unit
— 50 mA
— 60
— 100
— 45 mA
— 55
— 90
— 30
35
— 70
mA
20
— 25
— 60
mA
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  00B
04/23/08
5

5 Page





IS61WV25632ALL arduino
IS61WV25632ALL/ALS
IS61WV25632BLL/BLS
IS64WV25632BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol
twc
tsce
taw
tha
tsa
tpwb
tpwe1
tpwe2
tsd
thd
thzwe(2)
tlzwe(2)
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
BWa-d Valid to End of Write
WE Pulse Width
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
-8
Min. Max.
8 —
6.5 —
6.5 —
0 —
0 —
6.5 —
6.5 —
8.0 —
5 —
0 —
— 3.5
2 —
-10
Min. Max.
10 —
8 —
8 —
Unit
ns
ns
ns
0 —
ns
0 —
ns
8 —
ns
8 —
ns
10 —
ns
6 —
ns
0 — ­ns
— 5
ns
2 —
ns
Notes:
1.  Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and
output loading specified in Figure 1.
2.  Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3.  The internal write time is defined by the overlap of CE LOW, and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the write. Shaded area product in development
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  00B
04/23/08
11

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