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PDF IS64WV10248EDBLL Data sheet ( Hoja de datos )
| Número de pieza | IS64WV10248EDBLL | |
| Descripción | 1M x 8 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM | |
| Fabricantes | ISSI | |
| Logotipo |  |
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IS61WV10248EDBLL
IS64WV10248EDBLL
1M x 8 HIGH-SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH ECC
FEBRUARY 2013
FEATURES
• High-speed access times: 8, 10, 20 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE options
• CE power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Packages available:
– 48-ball miniBGA (6mm x 8mm)
– 44-pin TSOP (Type II)
• Industrial and Automotive Temperature Support
• Lead-free available
DESCRIPTION
The ISSI IS61/64WV10248EDBLL are very high-speed,
low power, 1M-word by 8-bit CMOS static RAM. The
IS61/64WV10248EDBLL are fabricated using ISSI's
high-performance CMOS technology. This highly reli-
able process coupled with innovative circuit design
techniques, yields higher performance and low power
consumption devices.
When CE is HIGH (deselected), the device assumes
a standby mode at which the power dissipation can be
reduced down with CMOS input levels.
The IS61/64WV10248EDBLL operate from a single
power supply and all inputs are TTL-compatible.
The IS61/64WV10248EDBLL are available in 48 ball
mini BGA (6mm x 8mm) and 44-pin TSOP (Type II)
packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A19
Decoder
Memory Array
(1024Kx8)
ECC Array
(1024Kx4)
IO0-7
8
I/O Data
Circuit
8
12
ECC
84
Column I/O
/CE
/OE
/WE
Control
Circuit
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. A
02/20/2013
1 page  
IS61WV10248EDBLL
IS64WV10248EDBLL
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 2.4V-3.6V
Symbol Parameter
Test Conditions
Voh
Vol
Output HIGH Voltage
Output LOW Voltage
Vdd = Min., Ioh = –1.0 mA
Vdd = Min., Iol = 1.0 mA
Vih
Input HIGH Voltage
Vil
Input LOW Voltage(1)
Ili
Input Leakage
GND ≤ Vin ≤ Vdd
Ilo
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width ≤ 2 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width ≤ 2 ns). Not 100% tested.
Min. Max. Unit
1.8 —
V
— 0.4 V
2.0 Vdd + 0.3 V
–0.3
0.8
V
–1 1 µA
–1 1 µA
AC TEST CONDITIONS (HIGH SPEED)
Parameter Unit
(2.4V-3.6V)
Input Pulse Level
0.4V to Vdd-0.3V
Input Rise and Fall Times
1.5ns
Input and Output Timing
and Reference Level (VRef)
Vdd/2
Output Load
See Figures 1 and 2
AC TEST LOADS
OUTPUT
ZO = 50Ω
50Ω
1.5V
30 pF
Including
jig and
scope
Figure 1.
3.3V
319 Ω
OUTPUT
5 pF
Including
jig and
scope
Figure 2.
353 Ω
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/20/2013
5
5 Page 
IS61WV10248EDBLL
IS64WV10248EDBLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol
Parameter
twc
Write Cycle Time
tsce
CE to Write End
taw
Address Setup Time
to Write End
tha
Address Hold from Write End
tsa
Address Setup Time
tpwe1
WE Pulse Width (OE = HIGH)
tpwe2
WE Pulse Width (OE = LOW)
tsd
Data Setup to Write End
thd
Data Hold from Write End
thzwe(2)
WE LOW to High-Z Output
tlzwe(2)
WE HIGH to Low-Z Output
-20 ns
Min. Max. Unit
20 —
ns
12 —
ns
12 —
ns
0 —
0 —
12 —
17 —
9 —
0 —
— 9
3 —
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test
Loads (Figure 1).
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and
Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
Integrated Silicon Solution, Inc. — www.issi.com 11
Rev. A
02/20/2013
11 Page | ||
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