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PDF IS66WVD2M16ALL Data sheet ( Hoja de datos )
| Número de pieza | IS66WVD2M16ALL | |
| Descripción | 32Mb Async and Burst CellularRAM | |
| Fabricantes | ISSI | |
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IS66WVD2M16ALL
32Mb Async and Burst CellularRAM 2.0
Overview
The IS66WVD2M16ALL is an integrated memory device containing 32Mbit Pseudo Static Random
Access Memory using a self-refresh DRAM array organized as 2M words by 16 bits. The device uses a
multiplexed address and data bus scheme to minimize pins and includes a industry standard burst
mode for increased read and write bandwidth. The device includes several power saving modes :
Reduced Array Refresh mode where data is retained in a portion of the array and Temperature
Controlled Refresh. Both these modes reduce standby current drain. The device can be operated in a
standard asynchronous mode and high performance burst mode. The die has separate power rails,
VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.
Features
Single device supports asynchronous and burst
operation
Mixed Mode supports asynchronous write and
synchronous read operation
Dual voltage rails for optional performance
VDD 1.7V~1.95V, VDDQ 1.7V~1.95V
Multiplexed address and data bus
ADQ0~ADQ15
Asynchronous mode read access : 70ns
Burst mode for Read and Write operation
4, 8, 16 or Continuous
Low Power Consumption
Asynchronous Operation < 25 mA
Burst operation < 35 mA (@104Mhz)
Standby < 150 uA(max.)
Deep power-down (DPD) < 3uA (Typ)
Low Power Feature
Reduced Array Refresh
Temperature Controlled Refresh
Operation Frequency up to 104MHz
Operating temperature Range
Industrial -40°C~85°C
Package: 54-ball VFBGA
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Rev.A | May 2011
www.issi.com - [email protected]
1
1 page  
IS66WVD2M16ALL
Functional Description
All functions for the device are listed below in Table 2.
Table 2. Functional Descriptions
Mode
Power
Asynchronous Mode
CLK1
ADV#
CE#
OE#
WE#
CRE2
UB#/
LB#
WAIT3
ADQ
[15:0]4
Note
Read
Active
L
LLH L
L
Low-Z
Data-out
5
Write
Active
L
LXL
L
L High-Z Data-in
5
Standby
Stand
by
L
X
HX X
L
X High-Z High-Z
6,7
No Operation
Idle
L
X
LXX
L
X Low-Z
X
5,7
Configuration
Register Write
Active
L
L H L H X High-Z High-Z
Configuration
Register Read
Active
L
L L H H L Low-Z Config-Reg
Out
Deep Power-
Down
DPD
L
X
HX X
X
X High-Z High-Z
10
Synchronous Mode (Burst Mode)
Async read
Active
L
LLH L
L Low-Z Data-Out 5
Async write Active
L
LXL
L
L High-Z Data-In
5
Stand
Standby
by
L
X HXX L
X High-Z High-Z
6,7
No operation
Idle
L
X
LXX
L
X Low-Z
X
5,8
Initial
burst read
Initial
burst write
Burst
continue
Active
Active
Active
L
LXH L
L
Low-Z
Address
5,8
L
LHL
L
X
Low-Z
Address
5,8
H
LXX
L
L
Low-Z
Data-In or
Data-Out
5,8
Burst suspend Active
L
L
LHX
L
X Low-Z High-Z 5,8
Configuration
register write
Configuration
register read
Deep Power-
Down
Active
Active
DPD
L
L LHL H
L LLHH
X HXX X
X
Low-Z
High-Z
8,11
L
Low-Z
Config-Reg
Out
8,11
X High-Z High-Z
10
Rev.A | May 2011
www.issi.com - [email protected]
5
5 Page 
IS66WVD2M16ALL
Asynchronous Mode
Asynchronous mode uses industry-standard SRAM control signals (CE#, ADV#, OE#,
WE#, UB#, and LB#). READ operations (Figure 4) are initiated by bringing CE#, ADV#,
UB# and LB# LOW while keeping OE# and WE# HIGH, and driving the address onto the
multiplexed address/data bus. ADV# is taken HIGH to capture the address, and OE# is
taken LOW. Valid data will be driven out of the I/Os after the specified access time has
elapsed.
WRITE operations (Figure 5) occur when CE#, ADV#, WE#, UB#, and LB# are driven LOW
with the address on the multiplexed address/data bus. ADV# is taken HIGH to capture
the address, then the write data is driven onto the bus. During asynchronous WRITE
operations, the OE# level is a “Don't Care,” and WE# will override OE#; however, OE#
must be HIGH while the address is driven onto the ADQ bus. The data to be written is
latched on the rising edge of CE#, WE#, UB#, and LB# (whichever occurs first).
During asynchronous operation, the CLK input must be held LOW. WAIT will be driven
during asynchronous READs, and its state should be ignored. WE# must not be held
LOW longer than tCEM.
Figure 4. Asynchronous Read Access Timing
Address
ADQ0-
ADQ15
ADV#
CE#
tAA
VALID
ADDRESS
tAVS
tAVH
VALID
ADDRESS
tVP
tAADV
tCVP tCO
UB#/LB#
OE#
WE#
WAIT
HiZ
tBA
tOLZ
tOE
tOEW
VALID
OUTPUT
tWZ
tHZ
tBHZ
tOHZ
HiZ
Rev.A | May 2011
www.issi.com - [email protected]
11
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