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IS66WVD1M16ALL の電気的特性と機能

IS66WVD1M16ALLのメーカーはISSIです、この部品の機能は「16Mb Async and Burst CellularRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS66WVD1M16ALL
部品説明 16Mb Async and Burst CellularRAM
メーカ ISSI
ロゴ ISSI ロゴ 




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IS66WVD1M16ALL Datasheet, IS66WVD1M16ALL PDF,ピン配置, 機能
IS66WVD1M16ALL
16Mb Async and Burst CellularRAM 2.0
Overview
The IS66WVD1M16ALL is an integrated memory device containing 16Mbit Pseudo Static Random
Access Memory using a self-refresh DRAM array organized as 1M words by 16 bits. The device uses a
multiplexed address and data bus scheme to minimize pins and includes a industry standard burst
mode for increased read and write bandwidth. The device includes several power saving modes :
Reduced Array Refresh mode where data is retained in a portion of the array and Temperature
Controlled Refresh. Both these modes reduce standby current drain. The device can be operated in a
standard asynchronous mode and high performance burst mode. The die has separate power rails,
VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.
Features
Single device supports asynchronous and burst
operation
Mixed Mode supports asynchronous write and
synchronous read operation
Dual voltage rails for optional performance
VDD 1.7V~1.95V, VDDQ 1.7V~1.95V
Multiplexed address and data bus
ADQ0~ADQ15
Asynchronous mode read access : 70ns
Burst mode for Read and Write operation
4, 8, 16 or Continuous
Low Power Consumption
Asynchronous Operation < 25 mA
Burst operation < 45 mA (@133Mhz)
Standby < 80 uA(max.)
Deep power-down (DPD) < 3uA (Typ)
Low Power Feature
Reduced Array Refresh
Temperature Controlled Refresh
Operation Frequency up to 133MHz
Operating temperature Range
Industrial -40°C~85°C
Package: 54-ball VFBGA
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Rev. A | July 2013
www.issi.com - [email protected]
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IS66WVD1M16ALL pdf, ピン配列
IS66WVD1M16ALL
54Ball VFBGA Ball Assignment
1 23 456
A
LB# OE#
NC
NC NC CRE
B
ADQ8 UB#
NC
NC CE# ADQ0
C
ADQ9 ADQ10 NC
NC ADQ1 ADQ2
D
VSSQ ADQ11 A17
NC ADQ3 VDD
E
VDDQ ADQ12 NC
A16 ADQ4 VSS
F
ADQ14 ADQ13 NC
NC ADQ5 ADQ6
G
ADQ15 A19
NC
NC WE# ADQ7
H
A18 NC
NC
NC NC NC
J
WAIT CLK ADV#
NC
NC
NC
[Top View]
(Ball Down)
Rev. A | July 2013
www.issi.com - [email protected]
3


3Pages


IS66WVD1M16ALL 電子部品, 半導体
IS66WVD1M16ALL
Notes
1. CLK must be LOW during Asynch Read and Asynch Write modes. CLK must be LOW to achieve
low standby current during standby mode and DPD modes. CLK must be static (LOW or HIGH)
during burst suspend.
2. Configuration registers are accessed when CRE is HIGH during the address portion
of a READ or WRITE cycle.
3. WAIT polarity is configured through the bus configuration register (BCR[10]).
4. When UB# and LB# are in select mode (LOW), ADQ0~ADQ15 are affected as shown.
When only LB# is in select mode, ADQ0~ADQ7 are affected as shown. When only UB# is
in select mode, ADQ8~ADQ15 are affected as shown.
5. The device will consume active power in this mode whenever addresses are changed with ADV#
LOW
6. When the device is in standby mode, address inputs and data inputs/outputs are internally
isolated from any external influence.
7. Vin=VDDQ or 0V, all device pins be static (unswitched) in order to achieve standby current.
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
9. Byte operation can be supported Write & Read at asynchronous mode and Write at
synchronous mode.
10. DPD is initiated when CE# transition from LOW to HIGH after writing RCR[4] to 0. DPD is
maintained until CE# transitions from HIGH to LOW
11. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW
for the equivalent of a single word burst (as indicated by WAIT).
Rev. A | July 2013
www.issi.com - [email protected]
6

6 Page



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部品番号部品説明メーカ
IS66WVD1M16ALL

16Mb Async and Burst CellularRAM

ISSI
ISSI


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