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PDF IS67WVC1M16ALL Data sheet ( Hoja de datos )
| Número de pieza | IS67WVC1M16ALL | |
| Descripción | 16Mb Async/Page/Burst CellularRAM | |
| Fabricantes | ISSI | |
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IS66WVC1M16ALL
IS67WVC1M16ALL
16Mb Async/Page/Burst CellularRAM 1.5
Overview
The IS66WVC1M16ALL and IS67WVC1M16ALL is an integrated memory device containing 16Mbit Pseudo
Static Random Access Memory using a self-refresh DRAM array organized as 1M words by 16 bits. The device
includes several power saving modes : Reduced Array Refresh mode where data is retained in a portion of
the array and Temperature Controlled Refresh. Both these modes reduce standby current drain. The device
can be operated in a standard asynchronous mode and high performance burst mode. The die has separate
power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.
Features
Single device supports asynchronous , page,
and burst operation
Mixed Mode supports asynchronous write and
synchronous read operation
Dual voltage rails for optional performance
VDD 1.7V~1.95V, VDDQ 1.7V~1.95V
Asynchronous mode read access : 70ns
Interpage Read access : 70ns
Intrapage Read access : 20ns
Burst mode for Read and Write operation
4, 8, 16,32 or Continuous
Low Power Consumption
Asynchronous Operation < 25 mA
Intrapage Read < 18mA
Burst operation < 45 mA (@133Mhz)
Standby < 80 uA(max.)
Deep power-down (DPD) < 3uA (Typ)
Low Power Feature
Reduced Array Refresh
Temperature Controlled Refresh
Deep power-down (DPD) mode
Operation Frequency up to 133Mhz
Operating temperature Range
Industrial: -40°C~85°C
Automotive A1: -40°C~85°C
Package: 54-ball VFBGA
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Rev.A | October 2013
1
1 page  
IS66WVC1M16ALL
IS67WVC1M16ALL
Functional Description
All functions for the device are listed below in Table 2.
Table 2. Functional Descriptions
Mode
Power
CLK1
ADV#
CE#
OE#
WE#
CRE2
UB#/
LB#
WAIT3
DQ
[15:0]4
Note
Asynchronous Mode
Read
Active
L
L
LLH
L
L
Low-Z
Data-out
5
Write
Active
L
L
LXL
L
L Low-Z Data-in
5
Standby
Stand
by
L
X HXX
L
X High-Z High-Z
6,7
No Operation
Idle
L
X
LXX
L
X Low-Z
X
5,7
Configuration
Register Write
Configuration
Register Read
Deep Power-
Down
Active
Active
DPD
L
L
L
L LHL H
L LLHH
X HXX X
X Low-Z High-Z
L
Low-Z
Config-Reg
Out
X High-Z High-Z
10
Synchronous Mode (Burst Mode)
Async read
Active
L
L
LLH
L
L
Low-Z
Data-Out
5
Async write
Active
L
L
LXL
L
L
Low-Z
Data-In
5
Standby
Stand
by
L
X HXX
L
X High-Z High-Z
6,7
No operation
Idle
L
X
LXX
L
X Low-Z
X
5,8
Initial
burst read
Initial
burst write
Burst
continue
Active
Active
Active
L L X H L L Low-Z X 5,8
L L H L L X Low-Z X 5,8
H
LXX
X
L
Low-Z
Data-In or
Data-Out
5,8
Burst suspend Active
X
X
LHX
X
X Low-Z High-Z 5,8
Configuration
register write
Configuration
register read
Deep Power-
Down
Active
Active
DPD
L
L LHL H
L LLHH
X HXX X
X
Low-Z
High-Z
8,11
L
Low-Z
Config-Reg
Out
8,11
X High-Z High-Z
10
Rev.A | October 2013
5
5 Page 
IS66WVC1M16ALL
IS67WVC1M16ALL
Asynchronous Mode
Asynchronous mode uses industry-standard SRAM control signals (CE#, OE#, WE#, UB#,
and LB#). READ operations (Figure 4) are initiated by bringing CE#, OE#, UB#/LB# LOW
while keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access
time has elapsed.
WRITE operations (Figure 5) occur when CE#, WE#, UB#/LB# are driven LOW. During
asynchronous WRITE operations, the OE# level is a “Don't Care,” and WE# will override
OE#. The data to be written is latched on the rising edge of CE#, WE#, UB#/LB#
(whichever occurs first). Asynchronous operations (page mode disabled) can either
use the ADV input to latch the address, or ADV can be driven LOW during the entire
READ/WRITE operations
During asynchronous operation, the CLK input must be held LOW. WAIT will be driven
during asynchronous READs, and its state should be ignored. WE# must not be held
LOW longer than tCEM.
Figure 4. Asynchronous Read Access Timing (ADV# LOW)
Address
tRC = READ cycle Time
VALID
ADDRESS
DQ0-
DQ15
CE#
UB#/LB#
OE#
WE#
Notes:
1. ADV must remain LOW for PAGE MODE operation.
VALID
OUTPUT
Rev.A | October 2013
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IS67WVC1M16ALL.PDF ] | |
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